| Line 66... |
Line 66... |
end component;
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end component;
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--! Ray Trac: Implementacion del Rt Engine
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--! Ray Trac: Implementacion del Rt Engine
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component raytrac
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component raytrac
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generic (
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generic (
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testbench_generation : string := "NO";
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registered : string := "NO" --! Este parametro, por defecto "YES", indica si se registran o cargan en registros los vectores A,B,C,D y los codigos de operacion opcode y addcode en vez de ser conectados directamente al circuito combinatorio. \n This parameter, by default "YES", indicates if vectors A,B,C,D and operation code inputs opcode are to be loaded into a register at the beginning of the pipe rather than just connecting them to the operations decoder (opcoder).
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registered : string := "NO" --! Este parametro, por defecto "YES", indica si se registran o cargan en registros los vectores A,B,C,D y los codigos de operacion opcode y addcode en vez de ser conectados directamente al circuito combinatorio. \n This parameter, by default "YES", indicates if vectors A,B,C,D and operation code inputs opcode are to be loaded into a register at the beginning of the pipe rather than just connecting them to the operations decoder (opcoder).
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);
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);
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port (
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port (
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A,B,C,D : in std_logic_vector(18*3-1 downto 0); --! Vectores de entrada A,B,C,D, cada uno de tamano fijo: 3 componentes x 18 bits. \n Input vectors A,B,C,D, each one of fixed size: 3 components x 18 bits.
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A,B,C,D : in std_logic_vector(18*3-1 downto 0); --! Vectores de entrada A,B,C,D, cada uno de tamano fijo: 3 componentes x 18 bits. \n Input vectors A,B,C,D, each one of fixed size: 3 components x 18 bits.
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opcode,addcode : in std_logic; --! Opcode and addcode input bits, opcode selects what operation is going to perform one of the entities included in the design and addcode what operands are going to be involved in such. \n Opcode & addcode, opcode selecciona que operacion se va a llevar a cabo dentro de una de las entidades referenciadas dentro de la descripcion, mientras que addcode decide cuales van a ser los operandos que realizaran tal.
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opcode,addcode : in std_logic; --! Opcode and addcode input bits, opcode selects what operation is going to perform one of the entities included in the design and addcode what operands are going to be involved in such. \n Opcode & addcode, opcode selecciona que operacion se va a llevar a cabo dentro de una de las entidades referenciadas dentro de la descripcion, mientras que addcode decide cuales van a ser los operandos que realizaran tal.
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| Line 108... |
Line 108... |
end component; --! Entidad uf: sus siglas significan undidad funcional. La unidad funcional se encarga de realizar las diferentes operaciones vectoriales (producto cruz — producto punto).
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end component; --! Entidad uf: sus siglas significan undidad funcional. La unidad funcional se encarga de realizar las diferentes operaciones vectoriales (producto cruz — producto punto).
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|
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component uf
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component uf
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generic (
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generic (
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use_std_logic_signed : string := "NO";
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use_std_logic_signed : string := "NO";
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testbench_generation : string := "NO";
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carry_logic : string := "CLA"
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carry_logic : string := "CLA"
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);
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);
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port (
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port (
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opcode : in std_logic;
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opcode : in std_logic;
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0);
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0);
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| Line 142... |
Line 143... |
a,b:in std_logic_vector(width-1 downto 0);
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a,b:in std_logic_vector(width-1 downto 0);
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s:in std_logic;
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s:in std_logic;
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c: out std_logic_vector(width-1 downto 0)
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c: out std_logic_vector(width-1 downto 0)
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);
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);
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end component;
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end component;
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|
|
|
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--! Esta entidad corresponde al multiplicador que se instanciar’a dentro de la unidad funcional. El multiplicador registra los operandos a la entrada y el respectivo producto de la multiplicaci—n a la salida.
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--! Esta entidad corresponde al multiplicador que se instanciar’a dentro de la unidad funcional. El multiplicador registra los operandos a la entrada y el respectivo producto de la multiplicaci—n a la salida.
|
component r_a18_b18_smul_c32_r
|
component lpm_mult
|
generic (
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generic (
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lpm_hint : string := "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9";
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lpm_hint : string;
|
lpm_pipeline : natural:= 2;
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lpm_pipeline : natural;
|
lpm_representation : string:="SIGNED";
|
lpm_representation : string;
|
lpm_type : string:="LPM_MULT";
|
lpm_type : string;
|
lpm_widtha : natural:=18;
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lpm_widtha : natural;
|
lpm_widthb : natural:=18;
|
lpm_widthb : natural;
|
lpm_widthp : natural:=32
|
lpm_widthp : natural
|
);
|
);
|
port (
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port (
|
aclr,clock:in std_logic;
|
aclr : in std_logic ;
|
dataa,datab:in std_logic_vector (17 downto 0);
|
clock : in std_logic ;
|
|
datab : in std_logic_vector (17 downto 0);
|
|
dataa : in std_logic_vector (17 downto 0);
|
result: out std_logic_vector(31 downto 0)
|
result: out std_logic_vector(31 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
|
|
|
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--! cla_logic_block corresponde a un bloque de l—gica Carry look Ahead. Se instancia y utiliza dentro de un sumador cualquiera, pues sirve para calcular los carry out de la operaci—n.
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--! cla_logic_block corresponde a un bloque de l—gica Carry look Ahead. Se instancia y utiliza dentro de un sumador cualquiera, pues sirve para calcular los carry out de la operaci—n.
|
component cla_logic_block
|
component cla_logic_block
|
generic ( width: integer:=4);
|
generic ( width: integer:=4);
|
port (
|
port (
|
p,g:in std_logic_vector(width-1 downto 0);
|
p,g:in std_logic_vector(width-1 downto 0);
|
| Line 205... |
Line 213... |
package body arithpack is
|
package body arithpack is
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--! Funciones utilitarias, relacionadas sobre todo con el testbench
|
--! Funciones utilitarias, relacionadas sobre todo con el testbench
|
constant hexchars : string (1 to 16) := "0123456789ABCDEF";
|
constant hexchars : string (1 to 16) := "0123456789ABCDEF";
|
|
|
procedure hexwrite_0(l:inout line;h:in std_logic_vector) is
|
procedure hexwrite_0(l:inout line;h:in std_logic_vector) is
|
variable index_high,index_low,acc : integer;
|
variable index_high,index_low,highone : integer;
|
|
|
begin
|
begin
|
for i in (h'high)/4 downto 0 loop
|
highone := h'high-h'low;
|
|
for i in (highone)/4 downto 0 loop
|
index_low:=i*4;
|
index_low:=i*4;
|
if (index_low+3)>h'high then
|
if (index_low+3)>highone then
|
index_high := h'high;
|
index_high := highone;
|
else
|
else
|
index_high := i*4+3;
|
index_high := i*4+3;
|
end if;
|
end if;
|
write(l,hexchars(1+ieee.std_logic_unsigned.conv_integer(h(index_high downto index_low))));
|
write(l,hexchars(1+ieee.std_logic_unsigned.conv_integer(h(index_high+h'low downto index_low+h'low))));
|
end loop;
|
end loop;
|
end procedure;
|
end procedure;
|
end package body arithpack;
|
end package body arithpack;
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No newline at end of file
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No newline at end of file
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