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[/] [raytrac/] [trunk/] [arithpack.vhd] - Diff between revs 59 and 60
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--! Biblioteca de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.
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--! Biblioteca de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.
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library ieee;
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library ieee;
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--! Paquete de definicion estandard de logica.
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--! Paquete de definicion estandard de logica.
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.math_real.all;
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--use ieee.std_logic_unsigned.conv_integer;
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--use ieee.std_logic_unsigned.conv_integer;
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--! Biblioteca de definicion de memorias de altera
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--! Biblioteca de definicion de memorias de altera
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component shifter is
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component shifter is
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generic (
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generic (
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address_width : integer := 9;
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address_width : integer := 9;
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width : integer := 12
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width : integer := 32;
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even_shifter : string := "YES"
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);
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);
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port (
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port (
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data : in std_logic_vector(width - 1 downto 0);
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data : in std_logic_vector(width - 1 downto 0);
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exp : out std_logic_vector(integer(ceil(log(real(width),2.0)))-1 downto 0);
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address : out std_logic_vector (address_width-1 downto 0);
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address : out std_logic_vector (address_width-1 downto 0);
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zero : out std_logic;
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zero : out std_logic
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maxoneispair : out std_logic
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);
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);
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end component;
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end component;
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