| Line 39... |
Line 39... |
);
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);
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end ema32x2;
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end ema32x2;
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architecture ema32x2_arch of ema32x2 is
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architecture ema32x2_arch of ema32x2 is
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component lpm_mult
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component shftr
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generic (
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lpm_hint : string;
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lpm_representation : string;
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lpm_type : string;
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lpm_widtha : natural;
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lpm_widthb : natural;
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lpm_widthp : natural
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);
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port (
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port (
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dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );
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dir : in std_logic;
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datab : in std_logic_vector ( lpm_widthb-1 downto 0 );
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places : in std_logic_vector (3 downto 0);
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result : out std_logic_vector( lpm_widthp-1 downto 0 )
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data24 : in std_logic_vector (23 downto 0);
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data40 : out std_logic_vector (39 downto 0)
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);
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);
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end component;
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end component;
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signal s2slr : std_logic_vector(1 downto 0);
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signal s2slr : std_logic_vector(1 downto 0);
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signal s3lshift,s4lshift : std_logic_vector(4 downto 0);
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signal s3lshift,s4lshift : std_logic_vector(4 downto 0);
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signal s2exp,s3exp,s4exp : std_logic_vector(7 downto 0);
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signal s0sdelta,s0udelta,s0udeltaa,s0udeltab,s2exp,s3exp,s4exp : std_logic_vector(7 downto 0);
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signal s4slab : std_logic_vector(15 downto 0);
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signal s4slab : std_logic_vector(15 downto 0);
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signal s2slab : std_logic_vector(16 downto 0);
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signal s2slab : std_logic_vector(16 downto 0);
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signal b1s,s4nrmP : std_logic_vector(22 downto 0); -- Inversor de la mantissa
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signal b1s,s4nrmP : std_logic_vector(22 downto 0); -- Inversor de la mantissa
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signal s0a,s0b,s1a,s1b : std_logic_vector(31 downto 0); -- Float 32 bit
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signal s0a,s0b,s1a,s1b : std_logic_vector(31 downto 0); -- Float 32 bit
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signal s1sma,s2sma,s2smb,s3sma,s3smb,s3ures,s4ures : std_logic_vector(24 downto 0); -- Signed mantissas
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signal s1sma,s2sma,s2smb,s3sma,s3smb,s3ures,s4ures : std_logic_vector(24 downto 0); -- Signed mantissas
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signal s3res : std_logic_vector(25 downto 0); -- Signed mantissa result
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signal s3res : std_logic_vector(25 downto 0); -- Signed mantissa result
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signal s1pS,s1pH,s1pL,s4nrmL,s4nrmH,s4nrmS : std_logic_vector(17 downto 0); -- Shifert Product
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signal s1pS,s1pH,s1pL,s4nrmL,s4nrmH,s4nrmS : std_logic_vector(17 downto 0); -- Shifert Product
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signal s0zeroa,s0zerob,s1z,s4sgr : std_logic;
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signal s0zeroa,s0zerob,s1zeroa,s1zerob,s1z,s4sgr : std_logic;
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begin
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begin
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process (clk)
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process (clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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--!Registro de entrada
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--!Registro de entrada
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s0a <= a32;
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s0a <= a32;
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s0b(31) <= dpc xor b32(31); --! Importante: Integrar el signo en el operando B
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s0b(31) <= dpc xor b32(31); --! Importante: Integrar el signo en el operando B
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s0b(30 downto 0) <= b32(30 downto 0);
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s0b(30 downto 0) <= b32(30 downto 0);
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s0b(22 downto 0) <= b32(22 downto 0);
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--!Etapa 0,Escoger el mayor exponente que sera el resultado desnormalizado, calcula cuanto debe ser el corrimiento de la mantissa con menor exponente y reorganiza los operandos, si el mayor es b, intercambia las posición si el mayor es a las posiciones la mantiene. Zero check.
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--!Etapa 0,Calcular la manera en que se llevara a cabo la desnormalizacion
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if s0a(30 downto 23) >= s0b (30 downto 23) then
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s1dira <= s0sdelta(7);
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--!signo,exponente,mantissa
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s1dirb <= not(s0sdelta(7));
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s1b(31) <= s0b(31);
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s1uma <= s0a(22 downto 0);
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s1b(30 downto 23) <= s0a(30 downto 23)-s0b(30 downto 23);
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s1umb <= s0b(22 downto 0);
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s1b(22 downto 0) <= s0b(22 downto 0);
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if s0zeroa='0' or s0zerob='0' then
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--! zero signaling
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s1expb <= s0b(30 downto 23) or s0a(30 downto 23);
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s1z <= s0zerob;
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s1udeltaa <= "0000";
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--!clasifica a
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s1udeltab <= "0000";
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s1a <= s0a;
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else
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else
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--!signo,exponente,mantissa
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s1expb <= s0b(30 downto 23);
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s1b(31) <= s0a(31);
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s1udeltaa <= s0udeltaa(3 downto 0);
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s1b(30 downto 23) <= s0b(30 downto 23)-s0a(30 downto 23);
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s1udeltab <= s1udeltab(3 downto 0);
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s1b(22 downto 0) <= s0a(22 downto 0);
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--! zero signaling
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s1z <= s0zeroa;
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--!clasifica b
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s1a <= s0b;
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end if;
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end if;
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s1zeroa <= s0zeroa;
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s1zerob <= s0zerob;
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--! Etapa 1: Denormalización de las mantissas.
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--! Etapa 1: Denormalización de las mantissas.
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--! A
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--! A
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s2exp <= s1a(30 downto 23);
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s2exp <= s1a(30 downto 23);
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s2sma <= s1sma;
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s2sma <= s1sma;
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| Line 171... |
Line 164... |
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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--! Combinatorial gremlin, Etapa 0, Escoger el mayor exponente que sera el resultado desnormalizado,\n
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--! Combinatorial gremlin, Etapa 0, Calcular la manera en que se llevara a cabo la desnormalizacion.
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--! calcula cuanto debe ser el corrimiento de la mantissa con menor exponente y reorganiza los operandos,\n
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--! si el mayor es b, intercambia las posición si el mayor es a las posiciones la mantiene. Zero check.\n
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process (s0b(30 downto 23),s0a(30 downto 23))
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process (s0b(30 downto 23),s0a(30 downto 23))
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begin
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begin
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s0zerob <='0';
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--! Diferencia signada entre el valor del exponente a y el exponente b
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s0sdelta <= s0a(30 downto 23) - s0b(30 downto 23);
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--! Manejo de cero
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if sa(30 downto 23) = "00000000" then
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s0zeroa <='0';
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s0zeroa <='0';
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for i in 30 downto 23 loop
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else
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if s0a(i)='1' then
|
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s0zeroa <= '1';
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s0zeroa <= '1';
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end if;
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end if;
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if s0b(i)='1' then
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if sb(30 downto 23) = "00000000" then
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s0zerob <= '0';
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else
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s0zerob <='1';
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s0zerob <='1';
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end if;
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end if;
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end process;
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process (s0sdelta)
|
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begin
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--! Esta parte define en que rango de la grafica de normalizacón se movera la normalizaci—n del resultado de la mantissa
|
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case s0sdelta(7 downto 1) is
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when "0000000" =>
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s0nrmshftype <= '0';
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when "1111111" =>
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s0nrmshftype <= not(s0sdelta(0));
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when others =>
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s0nrmshftype <= '1';
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end case;
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--! Valor absoluto de la diferencia entre el exponente a y el b
|
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for i in 7 downto 0 loop
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s0udelta(i) <= s0sdelta(7) xor s0sdelta(i);
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end loop;
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end loop;
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end process
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|
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process (s0udelta,s0sdelta(7))
|
|
begin
|
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s0udeltaa <= (s0udelta(7)&s0udelta(7 downto 1))+("0000000"&s0sdelta(7));
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s0udeltab <= (s0udelta(7)&s0udelta(7 downto 1))+("0000000"&s0udelta(0));
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end process;
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end process;
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--! Combinatorial Gremlin, Etapa 1 Denormalización de las mantissas.
|
--! Combinatorial Gremlin, Etapa 1 Denormalización de las mantissas.
|
denormsupershiftermult:lpm_mult
|
shftra:shftr
|
generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map (s1dira,s1udeltaa(2 downto 0),s1uma,
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port map ("00"&shl(conv_std_logic_vector(1,7),s1b(25 downto 23)),conv_std_logic_vector(0,3)&b1s(22 downto 17),s1pS);
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denormhighshiftermult:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map ("00"&shl(conv_std_logic_vector(1,7),s1b(25 downto 23)),b1s(16 downto 8),s1pH);
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denormlowshiftermult:lpm_mult
|
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
|
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port map ("00"&shl(conv_std_logic_vector(1,7),s1b(25 downto 23)),b1s(7 downto 0)&s1z,s1pL);
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s1b2b1s:
|
s1b2b1s:
|
for i in 22 downto 0 generate
|
for i in 22 downto 0 generate
|
b1s(i) <= s1b(22-i);
|
b1s(i) <= s1b(22-i);
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end generate s1b2b1s;
|
end generate s1b2b1s;
|
signa:
|
signa:
|
