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signal s0a,s0b,s1a,s1b : std_logic_vector(31 downto 0); -- Float 32 bit
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signal s0a,s0b,s1a,s1b : std_logic_vector(31 downto 0); -- Float 32 bit
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signal s1sma,s2sma,s2smb,s3sma,s3smb,s3ures,s4ures : std_logic_vector(24 downto 0); -- Signed mantissas
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signal s1sma,s2sma,s2smb,s3sma,s3smb,s3ures,s4ures : std_logic_vector(24 downto 0); -- Signed mantissas
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signal s3res : std_logic_vector(25 downto 0); -- Signed mantissa result
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signal s3res : std_logic_vector(25 downto 0); -- Signed mantissa result
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signal s1pS,s1pH,s1pL,s4nrmL,s4nrmH,s4nrmS : std_logic_vector(17 downto 0); -- Shifert Product
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signal s1pS,s1pH,s1pL,s4nrmL,s4nrmH,s4nrmS : std_logic_vector(17 downto 0); -- Shifert Product
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signal s0zeroa,s0zerob,s1zeroa,s1zerob,s1z,s4sgr : std_logic;
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signal s0zeroa,s0zerob,s1zeroa,s1zerob,s1z,s4sgr : std_logic;
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signal s2sma,s2smb : std_logic_vector (56 downto 0);
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begin
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begin
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process (clk)
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process (clk)
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begin
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begin
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s0b(31) <= dpc xor b32(31); --! Importante: Integrar el signo en el operando B
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s0b(31) <= dpc xor b32(31); --! Importante: Integrar el signo en el operando B
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s0b(30 downto 0) <= b32(30 downto 0);
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s0b(30 downto 0) <= b32(30 downto 0);
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s0b(22 downto 0) <= b32(22 downto 0);
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s0b(22 downto 0) <= b32(22 downto 0);
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--!Etapa 0,Calcular la manera en que se llevara a cabo la desnormalizacion
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--!Etapa 0,Calcular la manera en que se llevara a cabo la desnormalizacion
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s1signa <= s0a(31);
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s1signb <= s0b(31);
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s1dira <= s0sdelta(7);
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s1dira <= s0sdelta(7);
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s1dirb <= not(s0sdelta(7));
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s1uma <= s0a(22 downto 0);
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s1uma <= s0a(22 downto 0);
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s1umb <= s0b(22 downto 0);
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s1umb <= s0b(22 downto 0);
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if s0zeroa='0' or s0zerob='0' then
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if sa(30 downto 23) = "00000000" or sb(30 downto 23) = "00000000" then
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s1expb <= s0b(30 downto 23) or s0a(30 downto 23);
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s1expb <= s0b(30 downto 23) or s0a(30 downto 23);
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s1udeltaa <= "0000";
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s1udeltaa <= "0000";
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s1udeltab <= "0000";
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s1udeltab <= "0000";
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s1zero <= '1';
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else
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else
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s1expb <= s0b(30 downto 23);
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s1expb <= s0b(30 downto 23);
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s1udeltaa <= s0udeltaa(3 downto 0);
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s1udeltaa <= s0udeltaa(3 downto 0);
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s1udeltab <= s1udeltab(3 downto 0);
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s1udeltab <= s1udeltab(3 downto 0);
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s1zero <= '0';
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end if;
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end if;
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s1zeroa <= s0zeroa;
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s1zerob <= s0zerob;
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--! Etapa 1: Denormalización de las mantissas.
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--! Etapa 1: Denormalización de las mantissas.
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--! A
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--! A
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s2exp <= s1a(30 downto 23);
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s2exp <= s1a(30 downto 23);
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s2sma <= s1sma;
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s2sma <= s1sma;
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end process;
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end process;
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--! Combinatorial Gremlin, Etapa 1 Denormalización de las mantissas.
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--! Combinatorial Gremlin, Etapa 1 Denormalización de las mantissas.
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shftra:shftr
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shftra:shftr
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port map (s1dira,s1udeltaa(2 downto 0),s1uma,
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port map (s1dira,s1udeltaa(3 downto 0),'1'&s1uma,s1data40a);
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shftrb:shftr
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port map (not(s1dira),s1udeltab(3 downto 0),'1'&s1umb,s1data40b);
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process (s1data40b,s1data40a)
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begin
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if s1dira='1' then
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s1signeddata56a(55 downto 40) <= (others => '0');
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s1signeddata56b(15 downto 0) <= (others => '0');
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for i in 39 downto 0 loop
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s1signeddata56a(i) <= s1signa xor s1data40a(i);
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s1signeddata56b(i+16) <= s1signb xor s1data40b(i);
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end loop;
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else
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s1signeddata56a(15 downto 0) <= (others => '0');
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s1signeddata56b(55 downto 40) <= (others => '0');
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for i in 39 downto 0 loop
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s1signeddata56a(i+16) <= s1signa xor s1data40a(i);
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s1signeddata56b(i) <= s1signb xor s1data40b(i);
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end loop;
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end if;
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end process;
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s1b2b1s:
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s1b2b1s:
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for i in 22 downto 0 generate
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for i in 22 downto 0 generate
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b1s(i) <= s1b(22-i);
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b1s(i) <= s1b(22-i);
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end generate s1b2b1s;
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end generate s1b2b1s;
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