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------------------------------------------------
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--! @file ema32x3.vhd
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--! @brief RayTrac Exponent Managment Adder
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------
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-- RAYTRAC (FP BRANCH)
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-- Author Julian Andres Guarin
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-- ema32x3.vhd
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-- This file is part of raytrac.
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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entity ema32x3 is
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port (
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clk,dpc : in std_logic;
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a32,b32,c32 : in std_logic_vector (31 downto 0);
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res32 : out std_logic_vector (31 downto 0)
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);
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end ema32x3;
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architecture ema32x3_arch of ema32x3 is
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component lpm_mult
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generic (
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lpm_hint : string;
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lpm_representation : string;
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lpm_type : string;
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lpm_widtha : natural;
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lpm_widthb : natural;
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lpm_widthp : natural
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);
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port (
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dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );
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datab : in std_logic_vector ( lpm_widthb-1 downto 0 );
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result : out std_logic_vector( lpm_widthp-1 downto 0 )
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);
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end component;
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signal s2slrb,s2slrc : std_logic_vector(1 downto 0);
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signal s3lshift,s4lshift : std_logic_vector(4 downto 0);
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signal s2exp,s3exp,s4exp : std_logic_vector(7 downto 0);
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signal s4slab : std_logic_vector(15 downto 0);
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signal s2slabb,s2slabc : std_logic_vector(16 downto 0);
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signal b1s,c1s,s4nrmP : std_logic_vector(22 downto 0); -- Inversor de la mantissa
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signal s0a,s0b,s0c,s1a,s1b,s1c : std_logic_vector(31 downto 0); -- Float 32 bit
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signal s1sma,s2sma,s2smb,s2smc,s3sma,s3smb,s3smc : std_logic_vector(24 downto 0); -- Signed mantissas
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signal s3res : std_logic_vector(26 downto 0); -- Signed mantissa result
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signal s3ures,s4ures : std_logic_vector(25 downto 0);
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signal s1pSb,s1pHb,s1pLb,s1pSc,s1pHc,s1pLc,s4nrmL,s4nrmH,s4nrmS : std_logic_vector(17 downto 0); -- Shifert Product
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signal s0zeroa,s0zerob,s0zeroc,s1zb,s1zc,s4sgr : std_logic;
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begin
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process (clk)
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begin
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if clk'event and clk='1' then
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--!Registro de entrada
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s0a <= a32;
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s0b(31) <= dpc xor b32(31); --! Importante: Integrar el signo en el operando B
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s0b(30 downto 0) <= b32(30 downto 0);
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s0c <= c32;
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--!Etapa 0, Escoger el mayor exponente que sera el resultado desnormalizado, calcula cuanto debe ser el corrimiento de la mantissa con menor exponente y reorganiza los operandos, si el mayor es b, intercambia las posición si el mayor es a las posiciones la mantiene. Zero check.
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if s0a(30 downto 23) >= s0b (30 downto 23) and s0a(30 downto 23) >=s0c(30 downto 23) then
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--!signo,exponente,mantissa de b yc
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s1b(31) <= s0b(31);
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s1b(30 downto 23) <= s0a(30 downto 23) - s0b(30 downto 23);
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s1b(22 downto 0) <= s0b(22 downto 0);
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s1zb <= s0zerob;
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s1c(31) <= s0c(31);
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s1c(30 downto 23) <= s0a(30 downto 23) - s0c(30 downto 23);
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s1c(22 downto 0) <= s0c(22 downto 0);
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s1zc <= s0zeroc;
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--!clasifica a
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s1a <= s0a;
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elsif s0b(30 downto 23) >= s0c (30 downto 23) then
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--!signo,exponente,mantissa
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s1b(31) <= s0a(31);
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s1b(30 downto 23) <= s0b(30 downto 23)-s0a(30 downto 23);
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s1b(22 downto 0) <= s0a(22 downto 0);
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s1zb <= s0zeroa;
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s1c(31) <= s0c(31);
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s1c(30 downto 23) <= s0b(30 downto 23) - s0c(30 downto 23);
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s1c(22 downto 0) <= s0c(22 downto 0);
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s1zc <= s0zeroc;
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--!clasifica b
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s1a <= s0b;
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else
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--!signo,exponente,mantissa
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s1b(31) <= s0b(31);
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s1b(30 downto 23) <= s0c(30 downto 23)-s0b(30 downto 23);
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s1b(22 downto 0) <= s0b(22 downto 0);
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s1zb <= s0zerob;
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s1c(31) <= s0a(31);
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s1c(30 downto 23) <= s0c(30 downto 23) - s0a(30 downto 23);
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s1c(22 downto 0) <= s0a(22 downto 0);
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s1zc <= s0zeroa;
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--!clasifica c
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s1a <= s0c;
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end if;
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--! Etapa 1: Denormalización de las mantissas.
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--! A
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s2exp <= s1a(30 downto 23);
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s2sma <= s1sma;
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--! B & C
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for i in 23 downto 15 loop
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s2smb(i) <= s1pLb(23-i) xor s1b(31);
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s2smc(i) <= s1pLc(23-i) xor s1c(31);
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end loop;
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for i in 14 downto 6 loop
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s2smb(i) <= (s1pHc(14-i) or s1pLb(14-i+9)) xor s1b(31);
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s2smc(i) <= (s1pHc(14-i) or s1pLb(14-i+9)) xor s1c(31);
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end loop;
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for i in 5 downto 0 loop
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s2smb(i) <= (s1pSb(5-i) or s1pHb(5-i+9)) xor s1b(31);
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s2smc(i) <= (s1pSc(5-i) or s1pHc(5-i+9)) xor s1c(31);
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end loop;
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if s1b(30 downto 28)>"000" then
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s2slrb <= "11";
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else
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s2slrb <= s1b(27 downto 26);
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end if;
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if s1c(30 downto 28)>"000" then
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s2slrc <= "11";
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else
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s2slrc <= s1c(27 downto 26);
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end if;
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s2smb(24) <= s1b(31);
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s2smc(24) <= s1c(31);
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--! Etapa2: Finalizar la denormalización de b y c.
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--! A
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s3sma <= s2sma;
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s3exp <= s2exp;
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--! B
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case (s2slrb) is
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when "00" =>
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s3smb <= s2smb(24 downto 0)+s2smb(24);
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when "01" =>
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s3smb <= ( s2slabb(8 downto 0) & s2smb(23 downto 8) ) + s2smb(24);
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when "10" =>
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s3smb <= ( s2slabb(16 downto 0) & s2smb(23 downto 16)) + s2smb(24);
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when others =>
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s3smb <= (others => '0');
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end case;
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--! C
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case (s2slrc) is
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when "00" =>
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s3smc <= s2smc(24 downto 0)+s2smc(24);
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when "01" =>
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s3smc <= ( s2slabc(8 downto 0) & s2smc(23 downto 8) ) + s2smc(24);
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when "10" =>
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s3smc <= ( s2slabc(16 downto 0) & s2smc(23 downto 16)) + s2smc(24);
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when others =>
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s3smc <= (others => '0');
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end case;
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--! Etapa 3: Etapa 3 Realizar la suma, quitar el signo de la mantissa y codificar el corrimiento hacia la izquierda.
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s4ures <= s3ures+s3res(25); --Resultado no signado
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s4sgr <= s3res(25); --Signo
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s4exp <= s3exp; --Exponente
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s4lshift <= s3lshift; --Corrimiento hacia la izquierda.
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--! Etapa 4: Corrimiento y normalización de la mantissa resultado.
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res32(31) <= s4sgr;
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if s4ures(25)='1' then
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res32(22 downto 0) <= s4ures(24 downto 2);
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res32(30 downto 23) <= s4exp+2;
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elsif s4ures(24)='1' then
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res32(22 downto 0) <= s4ures(23 downto 1);
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res32(30 downto 23) <= s4exp+1;
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else
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case s4lshift(4 downto 3) is
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when "00" =>
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res32(22 downto 0) <= s4nrmP(22 downto 0);
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res32(30 downto 23) <= s4exp - s4lshift;
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when "01" =>
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res32(22 downto 0) <= s4nrmP(14 downto 0) & s4slab(7 downto 0);
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res32(30 downto 23) <= s4exp - s4lshift;
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when "10" =>
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res32(22 downto 0) <= s4nrmP(6 downto 0) & s4slab(15 downto 0);
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res32(30 downto 23) <= s4exp - s4lshift;
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when others =>
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res32(30 downto 0) <= (others => '0');
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end case;
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end if;
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end if;
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end process;
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--! Combinatorial gremlin, Etapa 0, Escoger el mayor exponente que sera el resultado desnormalizado,\n
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--! calcula cuanto debe ser el corrimiento de la mantissa con menor exponente y reorganiza los operandos,\n
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--! si el mayor es b, intercambia las posición si el mayor es a las posiciones la mantiene. Zero check.\n
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process (s0b(30 downto 23),s0a(30 downto 23),s0c(30 downto 23))
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begin
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s0zerob <='0';
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s0zeroa <='0';
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s0zeroc <='0';
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for i in 30 downto 23 loop
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if s0a(i)='1' then
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s0zeroa <= '1';
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end if;
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if s0b(i)='1' then
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s0zerob <='1';
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end if;
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if s0c(i)='1' then
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s0zeroc <='1';
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end if;
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end loop;
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end process;
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--! Combinatorial Gremlin, Etapa 1 Denormalización de las mantissas.
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denormsupershiftermultb:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map ("00"&shl(conv_std_logic_vector(1,7),s1b(25 downto 23)),conv_std_logic_vector(0,3)&b1s(22 downto 17),s1pSb);
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denormhighshiftermultb:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map ("00"&shl(conv_std_logic_vector(1,7),s1b(25 downto 23)),b1s(16 downto 8),s1pHb);
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denormlowshiftermultb:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map ("00"&shl(conv_std_logic_vector(1,7),s1b(25 downto 23)),b1s(7 downto 0)&s1zb,s1pLb);
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denormsupershiftermultc:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map ("00"&shl(conv_std_logic_vector(1,7),s1c(25 downto 23)),conv_std_logic_vector(0,3)&c1s(22 downto 17),s1pSc);
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denormhighshiftermultc:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map ("00"&shl(conv_std_logic_vector(1,7),s1c(25 downto 23)),c1s(16 downto 8),s1pHc);
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denormlowshiftermultc:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map ("00"&shl(conv_std_logic_vector(1,7),s1c(25 downto 23)),c1s(7 downto 0)&s1zc,s1pLc);
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s1b2b1s:
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for i in 22 downto 0 generate
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b1s(i) <= s1b(22-i);
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end generate s1b2b1s;
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s1c2c1s:
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for i in 22 downto 0 generate
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c1s(i) <= s1c(22-i);
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end generate s1c2c1s;
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signa:
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for i in 22 downto 0 generate
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s1sma(i) <= s1a(31) xor s1a(i);
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end generate;
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s1sma(23) <= not(s1a(31));
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s1sma(24) <= s1a(31);
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--! Combinatorial Gremlin, Etapa2: Finalizar la denormalización de b.
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s2signslab:
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for i in 16 downto 0 generate
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s2slabb(i) <= s2smb(24);
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s2slabc(i) <= s2smc(24);
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end generate s2signslab;
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--! Combinatorial Gremlin, Etapa 3 Realizar la suma, quitar el signo de la mantissa y codificar el corrimiento hacia la izquierda.
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--adder:sadd2
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--port map (s3sma(24)&s3sma,s3smb(24)&s3smb,dpc,s3res);
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process (s3sma,s3smb,s3smc)
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begin
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--! Magia: La suma ocurre aqui
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s3res <= (s3sma(24)&s3sma(24)&s3sma)+(s3smb(24)&s3smb(24)&s3smb)+(s3smc(24)&s3smc(24)&s3smc);
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end process;
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process(s3res)
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variable lshift : integer range 24 downto 0;
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begin
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lshift:=24;
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for i in 0 to 23 loop
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s3ures(i) <= s3res(26) xor s3res(i);
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if (s3res(26) xor s3res(i))='1' then
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lshift:=23-i;
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end if;
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end loop;
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s3ures(24) <= s3res(24) xor s3res(26);
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s3ures(25) <= s3res(25) xor s3res(26);
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s3lshift <= conv_std_logic_vector(lshift,5);
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end process;
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--! Combinatorial Gremlin, Etapa 4 corrimientos y normalización de la mantissa resultado.
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normsupershiftermult:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map (shl(conv_std_logic_vector(1,9),s4lshift(2 downto 0)),s4ures(22 downto 14),s4nrmS);
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normhighshiftermult:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map (shl(conv_std_logic_vector(1,9),s4lshift(2 downto 0)),s4ures(13 downto 5),s4nrmH);
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normlowshiftermult:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",9,9,18)
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port map (shl(conv_std_logic_vector(1,9),s4lshift(2 downto 0)),s4ures(4 downto 0)&conv_std_logic_vector(0,4),s4nrmL);
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process (s4nrmS,s4nrmH,s4nrmL)
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begin
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s4nrmP(22 downto 14) <= s4nrmS(8 downto 0) or s4nrmH(17 downto 9);
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s4nrmP(13 downto 5) <= s4nrmH(8 downto 0) or s4nrmL(17 downto 9);
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s4nrmP(4 downto 0) <= s4nrmL(8 downto 4);
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end process;
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s4signslab:
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for i in 15 downto 0 generate
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s4slab(i) <= '0';
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end generate s4signslab;
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end ema32x3_arch;
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