| Line 8... |
Line 8... |
entity sqrt32 is
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entity sqrt32 is
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port (
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port (
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|
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clk : in std_logic;
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clk : in std_logic;
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rd32: in std_logic_vector(31 downto 0);
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rd32: in std_logic_vector(31 downto 0);
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sq32: out std_logic_vector(31 downto 0)
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sq32: out std_logic_vector(31 downto 0)
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);
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);
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end sqrt32;
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end sqrt32;
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architecture sqrt32_arch of sqrt32 is
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architecture sqrt32_arch of sqrt32 is
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| Line 39... |
Line 38... |
address_a : in std_logic_vector (9 downto 0);
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address_a : in std_logic_vector (9 downto 0);
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q_a : out std_logic_vector (17 downto 0)
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q_a : out std_logic_vector (17 downto 0)
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);
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);
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end component;
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end component;
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signal s0nexp,s0uexp,s0e129,s0e1292 : std_logic_vector(30 downto 23);
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signal s0sgn : std_logic;
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signal s0uexp,s0e129 : std_logic_vector(7 downto 0);
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signal s0q : std_logic_vector(17 downto 0);
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signal s0q : std_logic_vector(17 downto 0);
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begin
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begin
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altsyncram_component : altsyncram
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altsyncram_component : altsyncram
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generic map (
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generic map (
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address_aclr_a => "NONE",
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => "../../../MinGW/msys/1.0/home/julian/code/testbench/trunk/fpbranch/sqrt/memsqrt.mif",
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init_file => "X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/fpbranch/sqrt/memsqrt.mif",
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intended_device_family => "Cyclone III",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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lpm_type => "altsyncram",
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numwords_a => 1024,
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numwords_a => 1024,
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operation_mode => "ROM",
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "CLOCK0",
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outdata_reg_a => "UNREGISTERED",
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widthad_a => 10,
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widthad_a => 10,
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width_a => 18,
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width_a => 18,
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width_byteena_a => 1
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width_byteena_a => 1
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)
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)
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port map (
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port map (
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clock0 => clk,
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clock0 => clk,
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address_a => s0uexp(0)&s0umr(22 downto 14),
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address_a => rd32(23 downto 14),
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q_a => s0q
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q_a => s0q
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);
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);
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--! SNAN?
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--! SNAN?
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process (clk)
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process (clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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|
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--!Carga de Operando.
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--!Carga de Operando.
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s0sgn<=rd(31);
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s0sgn <= rd32(31);
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s0uexp<=rd(30 downto 23);
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s0uexp <= rd32(30 downto 23);
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s0umr<=rd(22 downto 0);
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|
|
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--! Etapa 0: Calcular dirección a partir del exponente y el exponente.
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--! Etapa 0: Calcular dirección a partir del exponente y el exponente.
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sq32(31)<=s0sgn;
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sq32(31)<=s0sgn;
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sq32(22 downto 0)<=s0q(16 downto 0) & "000000";
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sq32(30 downto 23) <= (s0e129(7)&s0e129(7 downto 1))+127;
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sq32(22 downto 6) <= s0q(16 downto 0);
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|
|
|
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end if;
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end if;
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end process;
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end process;
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|
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--! Combinatorial Gremlin: Etapa 0, calculo del exponente.
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--! Combinatorial Gremlin: Etapa 0, calculo del exponente.
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s0e129<=s0uexp+129;
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s0e129<=s0uexp+("1000000"&s0uexp(0));
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s0e1292<=s0uexp(s0uexp'high)&s0uexp(7 downto 1);
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sq32(5 downto 0) <= (others => '0');
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|
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end sqrt32_arch;
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end sqrt32_arch;
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No newline at end of file
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No newline at end of file
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