| Line 44... |
Line 44... |
signal s0uexp,s0e129 : std_logic_vector(7 downto 0);
|
signal s0uexp,s0e129 : std_logic_vector(7 downto 0);
|
signal s0q : std_logic_vector(17 downto 0);
|
signal s0q : std_logic_vector(17 downto 0);
|
|
|
begin
|
begin
|
|
|
altsyncram_component : altsyncram
|
|
generic map (
|
|
address_aclr_a => "NONE",
|
|
clock_enable_input_a => "BYPASS",
|
|
clock_enable_output_a => "BYPASS",
|
|
init_file => "X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/fpbranch/sqrt/memsqrt.mif",
|
|
intended_device_family => "Cyclone III",
|
|
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
|
lpm_type => "altsyncram",
|
|
numwords_a => 1024,
|
|
operation_mode => "ROM",
|
|
outdata_aclr_a => "NONE",
|
|
outdata_reg_a => "UNREGISTERED",
|
|
widthad_a => 10,
|
|
width_a => 18,
|
|
width_byteena_a => 1
|
|
)
|
|
port map (
|
|
clock0 => clk,
|
|
address_a => rd32(23 downto 14),
|
|
q_a => s0q
|
|
);
|
|
--! SNAN?
|
--! SNAN?
|
process (clk)
|
process (clk)
|
begin
|
begin
|
if clk'event and clk='1' then
|
if clk'event and clk='1' then
|
|
|
| Line 88... |
Line 66... |
end process;
|
end process;
|
|
|
--! Combinatorial Gremlin: Etapa 0, calculo del exponente.
|
--! Combinatorial Gremlin: Etapa 0, calculo del exponente.
|
s0e129<=s0uexp+("1000000"&s0uexp(0));
|
s0e129<=s0uexp+("1000000"&s0uexp(0));
|
sq32(5 downto 0) <= (others => '0');
|
sq32(5 downto 0) <= (others => '0');
|
|
--! Combinatorial Gremlin, Etapa 0, calcula la raíz cuadrada de la mantissa
|
|
--! Recuerde que aunque rd32(23) no pertenece a la mantissa indica si el exponente es par o impar, 1 (par) y 0 (impar)
|
|
altsyncram_component : altsyncram
|
|
generic map (
|
|
address_aclr_a => "NONE",
|
|
clock_enable_input_a => "BYPASS",
|
|
clock_enable_output_a => "BYPASS",
|
|
init_file => "X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/fpbranch/sqrt/memsqrt.mif",
|
|
intended_device_family => "Cyclone III",
|
|
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
|
lpm_type => "altsyncram",
|
|
numwords_a => 1024,
|
|
operation_mode => "ROM",
|
|
outdata_aclr_a => "NONE",
|
|
outdata_reg_a => "UNREGISTERED",
|
|
widthad_a => 10,
|
|
width_a => 18,
|
|
width_byteena_a => 1
|
|
)
|
|
port map (clock0 => clk,address_a => rd32(23 downto 14),q_a => s0q);
|
|
|
end sqrt32_arch;
|
end sqrt32_arch;
|
No newline at end of file
|
No newline at end of file
|
