| Line 3... |
Line 3... |
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entity opcoder is
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entity opcoder is
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port (
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port (
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Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (17 downto 0);
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Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (17 downto 0);
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : out std_logic_vector (17 downto 0);
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : out std_logic_vector (17 downto 0);
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opcode,addcode : in std_logic
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opcode,addcode : in std_logic
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);
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);
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end entity;
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end entity;
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architecture opcoder_arch of opcoder is
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architecture opcoder_arch of opcoder is
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begin
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begin
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opcoder_:
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procOpcoder:
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process (Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz,opcode,addcode)
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process (Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz,opcode,addcode)
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variable scoder : std_logic_vector (1 downto 0);
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variable scoder : std_logic_vector (1 downto 0);
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begin
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begin
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scoder := opcode & addcode;
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scoder := opcode & addcode;
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case (scoder) is
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case (scoder) is
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when "0x" =>
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m0f0 <= Ax;
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m0f1 <= Bx;
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m1f0 <= Ay;
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m1f1 <= By;
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m2f0 <= Az;
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m2f1 <= Bz;
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m3f0 <= Cx;
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m3f1 <= Dx;
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m4f0 <= Cy;
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m4f1 <= Dy;
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m5f0 <= Cz;
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m5f1 <= Dz;
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when "10" =>
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when "10" =>
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m0f0 <= Ay;
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m0f0 <= Ay;
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m0f1 <= Bz;
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m0f1 <= Bz;
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m1f0 <= Az;
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m1f0 <= Az;
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m1f1 <= By;
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m1f1 <= By;
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| Line 58... |
Line 46... |
m4f0 <= Cx;
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m4f0 <= Cx;
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m4f1 <= Dy;
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m4f1 <= Dy;
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m5f0 <= Cy;
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m5f0 <= Cy;
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m5f1 <= Dx;
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m5f1 <= Dx;
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when others =>
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when others =>
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m0f0 <= ( others => '0');
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m0f0 <= Ax;
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m0f1 <= ( others => '0');
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m0f1 <= Bx;
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m1f0 <= ( others => '0');
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m1f0 <= Ay;
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m1f1 <= ( others => '0');
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m1f1 <= By;
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m2f0 <= ( others => '0');
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m2f0 <= Az;
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m2f1 <= ( others => '0');
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m2f1 <= Bz;
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m3f0 <= ( others => '0');
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m3f0 <= Cx;
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m3f1 <= ( others => '0');
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m3f1 <= Dx;
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m3f0 <= ( others => '0');
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m4f0 <= Cy;
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m3f1 <= ( others => '0');
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m4f1 <= Dy;
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m4f0 <= ( others => '0');
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m5f0 <= Cz;
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m4f1 <= ( others => '0');
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m5f1 <= Dz;
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m5f0 <= ( others => '0');
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m5f1 <= ( others => '0');
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end case;
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end case;
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end process opcoder_;
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end process procOpcoder;
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end opcoder_arch;
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end opcoder_arch;
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No newline at end of file
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No newline at end of file
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