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library ieee;
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library ieee;
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--! Paquete de manejo de logica estandard. \n Standard logic managment package.
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--! Paquete de manejo de logica estandard. \n Standard logic managment package.
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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--! The opcoder entity is the operation decoder combinatorial stage. \n La entidad opcoder es la etapa combinatoria que decodifica la operacion que se va a realizar.
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--! La entidad opcoder es la etapa combinatoria que decodifica la operacion que se va a realizar.
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--! The inputs to this hardware are: A,B,C,D vectors, opcode and add code inputs. The outputs are the operands of the 6 multipliers an uf entity has. The multipliers operands, also known as factors are m0f0 and m0f1 for the multiplier 0, m1f0 and m1f1 for the multiplier 1.. and so on until the multiplier 5. Basically what operates here in this description is a mux, which selects through opcode and addcode what vector components are going to be the multipliers operands.\n So if the opcode value is 0, it means that a dot product is to be done, so the m0f0 and m0f1 are going to be Ax and Bx respectively, and so on. If opcode is 1, it means that a cross product is to be performed, but the UF has only capacity to make a single cross product at --! the same time, meaning it will perform AxB OR CxD exclusively.\n\n In order to understand check the following table:
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--! \n\n
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--! Las entradas a esta descripción son: los vectores A,B,C,D, las entradas opcode y addcode. Las salidas del decodificador, estarán conectadas a las entradas de los 6 multiplicadores de una entidad uf. Los operandos de los multiplicadores, también conocidos como factores, son las salida m0f0, m0f1 para el multiplicador 1 y así hasta el multiplicador 5. Básicamente lo que opera aquí en esta descripción es un multiplexor, el cual selecciona a través de opcode y addcode qué componentes de los vectores se conectaran a los operandos de los multiplicadores.
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entity opcoder is
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entity opcoder is
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port (
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port (
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Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (17 downto 0);
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Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (17 downto 0);
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : out std_logic_vector (17 downto 0);
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : out std_logic_vector (17 downto 0);
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opcode,addcode : in std_logic
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opcode,addcode : in std_logic
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);
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);
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end entity;
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end entity;
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architecture opcoder_arch of opcoder is
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--! El bloque de arquitectura del decodificador es simplemente una cascada de multiplexores. La selección se hace en función de las señales appcode y addcode\n
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--! La siguiente tabla describe el comportamiento de los multiplexores:\n
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--! \n\n
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--!
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--! <table>
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--! <tr><th></th><th>OPCODE</th><th>ADDCODE</th><th>f0</th><th>f1</th><th> </th><th>OPCODE</th><th>ADDCODE</th><th>f0</th><th>f1</th><th> </th></tr> <tr><td>m0</td><td>0</td><td>0</td><td>Ax</td><td>Bx</td><td> </td><td>0</td><td>0</td><td>Cx</td><td>Dx</td><td>m3</td></tr> <tr><td>m0</td><td>0</td><td>1</td><td>Ax</td><td>Bx</td><td> </td><td>0</td><td>1</td><td>Cx</td><td>Dx</td><td>m3</td></tr> <tr><td>m0</td><td>1</td><td>0</td><td>Ay</td><td>Bz</td><td> </td><td>1</td><td>0</td><td>Ax</td><td>Bz</td><td>m3</td></tr> <tr><td>m0</td><td>1</td><td>1</td><td>Cy</td><td>Dz</td><td> </td><td>1</td><td>1</td><td>Cx</td><td>Dz</td><td>m3</td></tr> <tr><td>m1</td><td>0</td><td>0</td><td>Ay</td><td>By</td><td> </td><td>0</td><td>0</td><td>Cy</td><td>Dy</td><td>m4</td></tr> <tr><td>m1</td><td>0</td><td>1</td><td>Ay</td><td>By</td><td> </td><td>0</td><td>1</td><td>Cy</td><td>Dy</td><td>m4</td></tr> <tr><td>m1</td><td>1</td><td>0</td><td>Az</td><td>By</td><td> </td><td>1</td><td>0</td><td>Ax</td><td>By</td><td>m4</td></tr> <tr><td>m1</td><td>1</td><td>1</td><td>Cz</td><td>Dy</td><td> </td><td>1</td><td>1</td><td>Cx</td><td>Dy</td><td>m4</td></tr> <tr><td>m2</td><td>0</td><td>0</td><td>Az</td><td>Bz</td><td> </td><td>0</td><td>0</td><td>Cz</td><td>Dz</td><td>m5</td></tr> <tr><td>m2</td><td>0</td><td>1</td><td>Az</td><td>Bz</td><td> </td><td>0</td><td>1</td><td>Cz</td><td>Dz</td><td>m5</td></tr> <tr><td>m2</td><td>1</td><td>0</td><td>Az</td><td>Bx</td><td> </td><td>1</td><td>0</td><td>Ay</td><td>Bx</td><td>m5</td></tr> <tr><td>m2</td><td>1</td><td>1</td><td>Cz</td><td>Dx</td><td> </td><td>1</td><td>1</td><td>Cy</td><td>Dx</td><td>m5</td></tr></table>
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architecture opcoder_arch of opcoder is
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begin
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begin
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procOpcoder:
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procOpcoder:
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process (Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz,opcode,addcode)
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process (Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz,opcode,addcode)
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variable scoder : std_logic_vector (1 downto 0);
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variable scoder : std_logic_vector (1 downto 0);
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