| Line 1... |
Line 1... |
--! @file opcoder.vhd
|
--! @file opcoder.vhd
|
--! @brief Operation decoder. \n Decodificador de operacion.
|
--! @brief Decodificador de operacion.
|
|
--! @author Julián Andrés Guarín Reyes.
|
--------------------------------------------------------------
|
--------------------------------------------------------------
|
-- RAYTRAC
|
-- RAYTRAC
|
-- Author Julian Andres Guarin
|
-- Author Julian Andres Guarin
|
-- opcoder.vhd
|
-- opcoder.vhd
|
-- This file is part of raytrac.
|
-- This file is part of raytrac.
|
| Line 16... |
Line 17... |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
-- GNU General Public License for more details.
|
-- GNU General Public License for more details.
|
--
|
--
|
-- You should have received a copy of the GNU General Public License
|
-- You should have received a copy of the GNU General Public License
|
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
|
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
|
--! Libreria ieee. 'n Good oldie IEEE.
|
|
library ieee;
|
|
|
|
--! Paquete de manejo de logica estandard. \n Standard logic managment package.
|
|
|
--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
|
|
library ieee;
|
|
--! Paquete de definicion estandard de logica. Standard logic definition pack.
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
|
--! La entidad opcoder es la etapa combinatoria que decodifica la operacion que se va a realizar.
|
--! La entidad opcoder es la etapa combinatoria que decodifica la operacion que se va a realizar.
|
|
|
--! \n\n
|
--! \n\n
|
| Line 35... |
Line 37... |
|
|
opcode,addcode : in std_logic
|
opcode,addcode : in std_logic
|
);
|
);
|
end entity;
|
end entity;
|
|
|
|
--! Arquitectura del decodificador de operación.
|
|
|
--! El bloque de arquitectura del decodificador es simplemente una cascada de multiplexores. La selección se hace en función de las señales appcode y addcode\n
|
--! El bloque de arquitectura del decodificador es simplemente una cascada de multiplexores. La selección se hace en función de las señales appcode y addcode\n
|
--! La siguiente tabla describe el comportamiento de los multiplexores:\n
|
--! La siguiente tabla describe el comportamiento de los multiplexores:\n
|
--! \n\n
|
--! \n\n
|
|
|
--!
|
--!
|
--! <table>
|
--! <table>
|
--! <tr><th></th><th>OPCODE</th><th>ADDCODE</th><th>f0</th><th>f1</th><th> </th><th>OPCODE</th><th>ADDCODE</th><th>f0</th><th>f1</th><th> </th></tr> <tr><td>m0</td><td>0</td><td>0</td><td>Ax</td><td>Bx</td><td> </td><td>0</td><td>0</td><td>Cx</td><td>Dx</td><td>m3</td></tr> <tr><td>m0</td><td>0</td><td>1</td><td>Ax</td><td>Bx</td><td> </td><td>0</td><td>1</td><td>Cx</td><td>Dx</td><td>m3</td></tr> <tr><td>m0</td><td>1</td><td>0</td><td>Ay</td><td>Bz</td><td> </td><td>1</td><td>0</td><td>Ax</td><td>Bz</td><td>m3</td></tr> <tr><td>m0</td><td>1</td><td>1</td><td>Cy</td><td>Dz</td><td> </td><td>1</td><td>1</td><td>Cx</td><td>Dz</td><td>m3</td></tr> <tr><td>m1</td><td>0</td><td>0</td><td>Ay</td><td>By</td><td> </td><td>0</td><td>0</td><td>Cy</td><td>Dy</td><td>m4</td></tr> <tr><td>m1</td><td>0</td><td>1</td><td>Ay</td><td>By</td><td> </td><td>0</td><td>1</td><td>Cy</td><td>Dy</td><td>m4</td></tr> <tr><td>m1</td><td>1</td><td>0</td><td>Az</td><td>By</td><td> </td><td>1</td><td>0</td><td>Ax</td><td>By</td><td>m4</td></tr> <tr><td>m1</td><td>1</td><td>1</td><td>Cz</td><td>Dy</td><td> </td><td>1</td><td>1</td><td>Cx</td><td>Dy</td><td>m4</td></tr> <tr><td>m2</td><td>0</td><td>0</td><td>Az</td><td>Bz</td><td> </td><td>0</td><td>0</td><td>Cz</td><td>Dz</td><td>m5</td></tr> <tr><td>m2</td><td>0</td><td>1</td><td>Az</td><td>Bz</td><td> </td><td>0</td><td>1</td><td>Cz</td><td>Dz</td><td>m5</td></tr> <tr><td>m2</td><td>1</td><td>0</td><td>Az</td><td>Bx</td><td> </td><td>1</td><td>0</td><td>Ay</td><td>Bx</td><td>m5</td></tr> <tr><td>m2</td><td>1</td><td>1</td><td>Cz</td><td>Dx</td><td> </td><td>1</td><td>1</td><td>Cy</td><td>Dx</td><td>m5</td></tr></table>
|
--! <tr><th></th><th>OPCODE</th><th>ADDCODE</th><th>f0</th><th>f1</th><th> </th><th>OPCODE</th><th>ADDCODE</th><th>f0</th><th>f1</th><th> </th></tr> <tr><td>m0</td><td>0</td><td>0</td><td>Ax</td><td>Bx</td><td> </td><td>0</td><td>0</td><td>Cx</td><td>Dx</td><td>m3</td></tr> <tr><td>m0</td><td>0</td><td>1</td><td>Ax</td><td>Bx</td><td> </td><td>0</td><td>1</td><td>Cx</td><td>Dx</td><td>m3</td></tr> <tr><td>m0</td><td>1</td><td>0</td><td>Ay</td><td>Bz</td><td> </td><td>1</td><td>0</td><td>Ax</td><td>Bz</td><td>m3</td></tr> <tr><td>m0</td><td>1</td><td>1</td><td>Cy</td><td>Dz</td><td> </td><td>1</td><td>1</td><td>Cx</td><td>Dz</td><td>m3</td></tr> <tr><td>m1</td><td>0</td><td>0</td><td>Ay</td><td>By</td><td> </td><td>0</td><td>0</td><td>Cy</td><td>Dy</td><td>m4</td></tr> <tr><td>m1</td><td>0</td><td>1</td><td>Ay</td><td>By</td><td> </td><td>0</td><td>1</td><td>Cy</td><td>Dy</td><td>m4</td></tr> <tr><td>m1</td><td>1</td><td>0</td><td>Az</td><td>By</td><td> </td><td>1</td><td>0</td><td>Ax</td><td>By</td><td>m4</td></tr> <tr><td>m1</td><td>1</td><td>1</td><td>Cz</td><td>Dy</td><td> </td><td>1</td><td>1</td><td>Cx</td><td>Dy</td><td>m4</td></tr> <tr><td>m2</td><td>0</td><td>0</td><td>Az</td><td>Bz</td><td> </td><td>0</td><td>0</td><td>Cz</td><td>Dz</td><td>m5</td></tr> <tr><td>m2</td><td>0</td><td>1</td><td>Az</td><td>Bz</td><td> </td><td>0</td><td>1</td><td>Cz</td><td>Dz</td><td>m5</td></tr> <tr><td>m2</td><td>1</td><td>0</td><td>Az</td><td>Bx</td><td> </td><td>1</td><td>0</td><td>Ay</td><td>Bx</td><td>m5</td></tr> <tr><td>m2</td><td>1</td><td>1</td><td>Cz</td><td>Dx</td><td> </td><td>1</td><td>1</td><td>Cy</td><td>Dx</td><td>m5</td></tr></table>
|
|
--! \n\n
|
|
--! Por ejemplo para ver la tabla de verdad del m0f0, consultar el registro (línea) m0 y el atributo (columna) f0.\n
|
|
|
architecture opcoder_arch of opcoder is
|
architecture opcoder_arch of opcoder is
|
|
|
begin
|
begin
|
|
--! Proceso que describe las 2 etapas de multiplexores.
|
|
--! Proceso que describe las 2 etapas de multiplexores. Una corresponde al selector addcode, que selecciona con que operadores realizará la operación producto cruz, es decir, seleccionará si realiza la operación AxB ó CxD. En el caso del producto punto, esta etapa de multiplexación no tendrá repercusión en el resultado de la deocdificación de la operación. La otra etapa utiliza el selector opcode, el cual decide si usa los operandos decodificados en la primera etapa de multiplexores, en el caso de que opcode sea 1, seleccionando la operación producto cruz, o por el contrario seleccionando una decodificación de operadores que lleven a cabo la operación producto punto.
|
|
|
procOpcoder:
|
procOpcoder:
|
process (Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz,opcode,addcode)
|
process (Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz,opcode,addcode)
|
variable scoder : std_logic_vector (1 downto 0);
|
variable scoder : std_logic_vector (1 downto 0);
|
begin
|
begin
|
