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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac/] [trunk/] [raytrac.vhd] - Diff between revs 11 and 14

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Rev 11 Rev 14
Line 28... Line 28...
        );
        );
        port (
        port (
                A,B,C,D                 : in std_logic_vector(18*3-1 downto 0);
                A,B,C,D                 : in std_logic_vector(18*3-1 downto 0);
                opcode,addcode  : in std_logic;
                opcode,addcode  : in std_logic;
                clk,rst,ena             : in std_logic;
                clk,rst,ena             : in std_logic;
                CPX,CPY,CPZ,DP0,DP1 : out std_logic_vector(31 downto 0);
                CPX,CPY,CPZ,DP0,DP1 : out std_logic_vector(31 downto 0)
 
 
 
 
        );
        );
end raytrac;
end raytrac;
 
 
architecture raytrac_arch of raytrac is
architecture raytrac_arch of raytrac is
Line 52... Line 53...
                sopcode <= opcode;
                sopcode <= opcode;
                saddcode <= addcode;
                saddcode <= addcode;
        end generate notreg;
        end generate notreg;
        reg:
        reg:
        if registered="YES" generate
        if registered="YES" generate
                _oreg:
                procReg:
                process(clk,rst)
                process(clk,rst)
                begin
                begin
                        if rst=rstMasterValue then
                        if rst=rstMasterValue then
                                SA <= (others => '0');
                                SA <= (others => '0');
                                SB <= (others => '0');
                                SB <= (others => '0');
                                SC <= (others => '0');
                                SC <= (others => '0');
                                SD <= (others => '0');
                                SD <= (others => '0');
                                sopcode <= (others =>'0');
                                sopcode <= '0';
                                saddcode <= (others => '0');
                                saddcode <= '0';
                        elsif clk'event and clk='1' then
                        elsif clk'event and clk='1' then
                                if ena <= '1' then
                                if ena <= '1' then
                                        SA <= A;
                                        SA <= A;
                                        SB <= B;
                                        SB <= B;
                                        SC <= C;
                                        SC <= C;
                                        SD <= D;
                                        SD <= D;
                                        sopcode <= opcode;
                                        sopcode <= opcode;
                                        saddcode <= addcode;
                                        saddcode <= addcode;
                                end if;
                                end if;
                        end if;
                        end if;
                end process _oreg;
                end process procReg;
        end generate reg;
        end generate reg;
        -- Instantiate Opcoder 
        -- Instantiate Opcoder 
        opcdr : opcoder
        opcdr : opcoder
        port map (
        port map (
                SA(17 downto 0),SB(17 downto 0),SC(17 downto 0),SD(17 downto 0),SA(35 downto 18),SB(35 downto 18),SC(35 downto 18),SD(35 downto 18),SA(53 downto 36),SB(53 downto 36),SC(53 downto 36),SD(53 downto 36),
                SA(17 downto 0),SB(17 downto 0),SC(17 downto 0),SD(17 downto 0),SA(35 downto 18),SB(35 downto 18),SC(35 downto 18),SD(35 downto 18),SA(53 downto 36),SB(53 downto 36),SC(53 downto 36),SD(53 downto 36),

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