| Line 96... |
Line 96... |
);
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);
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port (
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port (
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A,B,C,D : in std_logic_vector(18*3-1 downto 0); --! Vectores de entrada A,B,C,D, cada uno de tamano fijo: 3 componentes x 18 bits. \n Input vectors A,B,C,D, each one of fixed size: 3 components x 18 bits.
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A,B,C,D : in std_logic_vector(18*3-1 downto 0); --! Vectores de entrada A,B,C,D, cada uno de tamano fijo: 3 componentes x 18 bits. \n Input vectors A,B,C,D, each one of fixed size: 3 components x 18 bits.
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opcode,addcode : in std_logic; --! Opcode and addcode input bits, opcode selects what operation is going to perform one of the entities included in the design and addcode what operands are going to be involved in such. \n Opcode & addcode, opcode selecciona que operacion se va a llevar a cabo dentro de una de las entidades referenciadas dentro de la descripcion, mientras que addcode decide cuales van a ser los operandos que realizaran tal.
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opcode,addcode : in std_logic; --! Opcode and addcode input bits, opcode selects what operation is going to perform one of the entities included in the design and addcode what operands are going to be involved in such. \n Opcode & addcode, opcode selecciona que operacion se va a llevar a cabo dentro de una de las entidades referenciadas dentro de la descripcion, mientras que addcode decide cuales van a ser los operandos que realizaran tal.
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clk,rst,ena : in std_logic; --! Las senales de control usual. The usual control signals.
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clk,rst,ena : in std_logic; --! Las senales de control usual. The usual control signals.
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sqrt0,sqrt1 : out std_logic_vector(17 downto 0);
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addABx,addABy,addABz,addCDx,addCDy,addCDz : out std_logic_vector(17 downto 0);--! Suma de vectores.
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addABx,addABy,addABz,addCDx,addCDy,addCDz : out std_logic_vector(17 downto 0);--! Suma de vectores.
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subABx,subABy,subABz,subCDx,subCDy,subCDz : out std_logic_vector(17 downto 0);--! Suma de vectores.
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subABx,subABy,subABz,subCDx,subCDy,subCDz : out std_logic_vector(17 downto 0);--! Suma de vectores.
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CPX,CPY,CPZ,DP0,DP1,kvx0,kvy0,kvz0,kvx1,kvy1,kvz1 : out std_logic_vector(31 downto 0);--! Salidas que representan los resultados del RayTrac: pueden ser dos resultados, de dos operaciones de producto punto, o un producto cruz. Por favor revisar el documento de especificacion del dispositivo para tener mas claridad.\n Outputs representing the result of the RayTrac entity: can be the results of two parallel dot product operations or the result of a single cross product, in order to clarify refere to the entity specification documentation.
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CPX,CPY,CPZ,DP0,DP1,kvx0,kvy0,kvz0,kvx1,kvy1,kvz1 : out std_logic_vector(31 downto 0) --! Salidas que representan los resultados del RayTrac: pueden ser dos resultados, de dos operaciones de producto punto, o un producto cruz. Por favor revisar el documento de especificacion del dispositivo para tener mas claridad.\n Outputs representing the result of the RayTrac entity: can be the results of two parallel dot product operations or the result of a single cross product, in order to clarify refere to the entity specification documentation.
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);
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);
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end raytrac;
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end raytrac;
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| Line 170... |
Line 171... |
sopcode <= opcode;
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sopcode <= opcode;
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saddcode <= addcode;
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saddcode <= addcode;
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end process procNotReg;
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end process procNotReg;
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end generate notreg;
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end generate notreg;
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--! El siguiente sumador es un sumador de 18 bits por lo tanto no se utiliza el sumador de 32 bits en la etapa SR del UF.
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--! El siguiente sumador es un sumador de 18 bits por lo tanto no se utiliza el sumador de 32 bits en la etapa SR del UF.
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procaddsub:
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process (clk,rst,SA,SB,SC,SD)
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begin
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if rst=rstMasterValue then
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addABx <= (others => '0');
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addABy <= (others => '0');
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addABz <= (others => '0');
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subABx <= (others => '0');
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subABy <= (others => '0');
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subABz <= (others => '0');
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elsif clk'event and clk='1' then
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addABx <= SA(17 downto 0) + SB(17 downto 0);
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addABx <= SA(17 downto 0) + SB(17 downto 0);
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addABy <= SA(35 downto 18) + SB(35 downto 18);
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addABy <= SA(35 downto 18) + SB(35 downto 18);
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addABz <= SA(53 downto 36) + SB(53 downto 36);
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addABz <= SA(53 downto 36) + SB(53 downto 36);
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addCDx <= SC(17 downto 0) + SD(17 downto 0);
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addCDx <= SC(17 downto 0) + SD(17 downto 0);
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addCDy <= SC(35 downto 18) + SD(35 downto 18);
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addCDy <= SC(35 downto 18) + SD(35 downto 18);
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| Line 182... |
Line 196... |
subABy <= SA(35 downto 18) - SB(35 downto 18);
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subABy <= SA(35 downto 18) - SB(35 downto 18);
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subABz <= SA(53 downto 36) - SB(53 downto 36);
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subABz <= SA(53 downto 36) - SB(53 downto 36);
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subCDx <= SC(17 downto 0) - SD(17 downto 0);
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subCDx <= SC(17 downto 0) - SD(17 downto 0);
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subCDy <= SC(35 downto 18) - SD(35 downto 18);
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subCDy <= SC(35 downto 18) - SD(35 downto 18);
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subCDz <= SC(53 downto 36) - SD(53 downto 36);
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subCDz <= SC(53 downto 36) - SD(53 downto 36);
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end if;
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end process procaddsub;
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--! Instantiate Opcoder
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--! Instantiate Opcoder
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opcdr : opcoder
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opcdr : opcoder
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port map (
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port map (
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