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Line 18... |
--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.math_real.all;
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use ieee.math_real.all;
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| Line 31... |
Line 31... |
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entity sqrtdiv is
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entity sqrtdiv is
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generic (
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generic (
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reginput: string := "YES";
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reginput: string := "YES";
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c3width : integer := 18;
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c3width : integer := 18;
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functype: string := "SQUARE_ROOT";
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functype: string := "INVERSION";
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iwidth : integer := 32;
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iwidth : integer := 32;
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owidth : integer := 16;
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owidth : integer := 18;
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awidth : integer := 9
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awidth : integer := 9
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);
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);
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port (
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port (
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clk,rst : in std_logic;
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clk,rst : in std_logic;
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value : in std_logic_vector (iwidth-1 downto 0);
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value : in std_logic_vector (iwidth-1 downto 0);
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| Line 67... |
Line 67... |
signal cumpaexp : std_logic_vector (2*integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
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signal cumpaexp : std_logic_vector (2*integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
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signal cumpaq : std_logic_vector (2*c3width-1 downto 0);
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signal cumpaq : std_logic_vector (2*c3width-1 downto 0);
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signal cumpaselector : std_logic;
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signal cumpaselector : std_logic;
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signal cumpazero : std_logic;
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signal cumpazero : std_logic;
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signal cumpaN : std_logic_vector (2*integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
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signal cumpaN : std_logic_vector (integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
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signal cumpaF : std_logic_vector (c3width-1 downto 0);
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signal cumpaF : std_logic_vector (c3width-1 downto 0);
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--! chief::Cuarta etapa: Corrimiento a la izquierda o derecha, para el caso de la ra'iz cuadrada o la inversi'on respectivamente.
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--! chief::Cuarta etapa: Corrimiento a la izquierda o derecha, para el caso de la ra'iz cuadrada o la inversi'on respectivamente.
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signal chiefN : std_logic_vector (2*integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
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signal chiefN : std_logic_vector (integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
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signal chiefF : std_logic_vector (c3width-1 downto 0);
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signal chiefF : std_logic_vector (c3width-1 downto 0);
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--! Constantes para manejar el tamaño de los vectores
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constant exp1H : integer := 2*integer(ceil(log(real(iwidth),2.0)))-1;
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constant exp1L : integer := integer(ceil(log(real(iwidth),2.0)));
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constant exp0H : integer := exp1L-1;
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constant exp0L : integer := 0;
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constant add1H : integer := 2*awidth-1;
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constant add1L : integer := awidth;
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constant add0H : integer := add1L-1;
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constant add0L : integer := 0;
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constant c3qHH : integer := 2*c3width-1;
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constant c3qHL : integer := c3width;
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constant c3qLH : integer := c3width-1;
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constant c3qLL : integer := 0;
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begin
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begin
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!-- expomantis.
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--! expomantis.
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expomantisreg:
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expomantisreg:
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if reginput="YES" generate
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if reginput="YES" generate
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expomantisProc:
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expomantisProc:
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process (clk,rst)
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process (clk,rst)
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begin
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begin
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if rst=rstMasterValue then
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if rst=rstMasterValue then
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expomantisvalue <= (others =>'0');
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expomantisvalue <= (others =>'0');
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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expomantisvalue <= vale;
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expomantisvalue <= value;
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end if;
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end if;
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end process expomantisProc;
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end process expomantisProc;
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end generate expomantisreg;
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end generate expomantisreg;
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expomantisnoreg;
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expomantisnoreg:
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if reginput ="NO" generate
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if reginput ="NO" generate
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expomantisvalue<=value;
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expomantisvalue<=value;
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end generate expomantisnoreg;
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end generate expomantisnoreg;
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expomantisshifter2x:shifter2xstage
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expomantisshifter2x:shifter2xstage
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generic map(awidth,iwidth)
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generic map(awidth,iwidth)
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port map(expomantisvalue,expomantisexp,expomantisadd,expomantiszero);
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port map(expomantisvalue,expomantisexp,expomantisadd,expomantiszero);
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--! funky.
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--! funky.
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funkyProc:
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funkyProc:
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process (clk,rst)
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process (clk,rst,expomantisexp, expomantiszero)
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begin
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begin
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if rst=rstMasterValue then
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if rst=rstMasterValue then
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funkyexp <= (others => '0');
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funkyexp <= (others => '0');
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funkyzero <= '0';
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funkyzero <= '0';
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else
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elsif clk'event and clk='1' then
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funkyexp <= expomantisexp;
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funkyexp(exp1H downto 0) <= expomantisexp(exp1H downto 0);
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funkyzero <= expomantiszero;
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funkyzero <= expomantiszero;
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end if;
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end if;
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end process funkyProc;
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end process funkyProc;
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funkyadd <= expomantisadd;
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funkyadd <= expomantisadd;
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funkyget:
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funkyget:
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process (funkyexp)
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process (funkyexp)
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begin
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begin
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if (funkyexp(integer(ceil(log(real(iwidth),2.0)))-1 downto 0)>funkyexp(2*integer(ceil(log(real(iwidth),2.0)))-1 downto integer(ceil(log(real(iwidth),2.0))))) then
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if (funkyexp(exp0H downto 0)>funkyexp(exp1H downto exp1L)) then
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funkyselector<='0';
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funkyselector<='0';
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else
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else
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funkyselector<='1';
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funkyselector<='1';
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end if;
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end if;
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end process funkyget;
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end process funkyget;
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funkyinversion:
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funkyinversion:
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if functype="INVERSION" generate
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if functype="INVERSION" generate
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meminvr:func
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meminvr:func
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generic map ("X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/meminvr.mif")
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generic map ("X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/meminvr.mif")
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port map(
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port map(
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funkyadd(integer(ceil(log(real(iwidth),2.0)))-1 downto 0),
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funkyadd(add0H downto add0L),
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funkyadd(2*integer(ceil(log(real(iwidth),2.0)))-1 downto integer(ceil(log(real(iwidth),2.0)))),
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funkyadd(add1H downto add1L),
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clk,
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clk,
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funkyq(c3width-1 downto 0),
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funkyq(c3qLH downto c3qLL),
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funkyq(2*c3width-1 downto c3width));
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funkyq(c3qHH downto c3qHL));
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end generate funkyinversion;
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end generate funkyinversion;
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funkysquare_root:
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funkysquare_root:
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if functype="SQUARE_ROOT" generate
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if functype="SQUARE_ROOT" generate
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sqrt: func
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sqrt: func
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generic map ("X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt.mif")
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generic map ("X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt.mif")
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port map(
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port map(
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funkyadd(integer(ceil(log(real(iwidth),2.0)))-1 downto 0),
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funkyadd(add0H downto add0L),
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ad1 => (others => '0'),
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(others => '0'),
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clk,
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clk,
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funkyq(c3width-1 downto 0),
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funkyq(c3qLH downto c3qLL),
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open);
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open);
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sqrt2x: func
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sqrt2x: func
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generic map ("X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt2f.mif")
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generic map ("X:/Tesis/Workspace/hw/rt_lib/arith/src/trunk/sqrtdiv/memsqrt2f.mif")
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port map(
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port map(
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ad0 => (others => '0'),
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(others => '0'),
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funkyadd(2*integer(ceil(log(real(iwidth),2.0)))-1 downto integer(ceil(log(real(iwidth),2.0)))),
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funkyadd(add1H downto add1L),
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clk,
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clk,
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open,
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open,
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funkyq(2*c3width-1 downto c3width));
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funkyq(c3qHH downto c3qHL));
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end generate funkysquare_root;
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end generate funkysquare_root;
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--! cumpa.
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--! cumpa.
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cumpaProc:
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cumpaProc:
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process (clk,rst)
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process (clk,rst)
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begin
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begin
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if rst=rstMasterValue then
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if rst=rstMasterValue then
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cumpaselector <= (others => '0');
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cumpaselector <= '0';
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cumpazero <= (others => '0');
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cumpazero <= '0';
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cumpaexp <= (others => '0');
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cumpaexp <= (others => '0');
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cumpaq <= (others => '0');
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cumpaq <= (others => '0');
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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cumpaselector <= funkyselector;
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cumpaselector <= funkyselector;
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cumpazero <= funkyzero;
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cumpazero <= funkyzero;
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| Line 175... |
Line 192... |
end process cumpaProc;
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end process cumpaProc;
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cumpaMux:
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cumpaMux:
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process (cumpaq,cumpaexp,cumpaselector)
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process (cumpaq,cumpaexp,cumpaselector)
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begin
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begin
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if cumpaselector='0' then
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if cumpaselector='0' then
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cumpaN<=cumpaexp(integer(ceil(log(real(iwidth),2.0)))-1 downto 0);
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cumpaN<=cumpaexp(exp0H downto exp0L);
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cumpaF<=cumpaq(c3width-1 downto 0);
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cumpaF<=cumpaq(c3qLH downto c3qLL);
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else
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else
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cumpaN<=cumpaexp(2*integer(ceil(log(real(iwidth),2.0)))-1 downto integer(ceil(log(real(iwidth),2.0))));
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cumpaN<=cumpaexp(exp1H downto exp1L);
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cumpaF<=cumpaq(2*c3width-1 downto c3width);
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cumpaF<=cumpaq(c3qHH downto c3qHL);
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end if;
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end if;
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end process cumpaMux;
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end process cumpaMux;
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--! chief.
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--! chief.
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chiefProc:
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chiefProc:
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| Line 196... |
Line 213... |
chiefF <= cumpaF;
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chiefF <= cumpaF;
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chiefN <= cumpaN;
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chiefN <= cumpaN;
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zero <= cumpazero;
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zero <= cumpazero;
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end if;
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end if;
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end process chiefProc;
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end process chiefProc;
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cumpaShifter: RLshifter
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chiefShifter: RLshifter
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generic map(functype,c3width,owidth)
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generic map(functype,c3width,iwidth,owidth)
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port map(chiefN,chiefF,result);
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port map(
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chiefN,
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chiefF,
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result);
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end sqrtdiv_arch;
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end sqrtdiv_arch;
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