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------------------------------------------------
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--! @file tb.vhd
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--! @brief RayTrac TestBench
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- tb.vhd
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-- This file is part of raytrac.
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use std.textio.all;
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use work.arithpack.all;
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entity tb is
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end tb;
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architecture tb_arch of tb is
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signal qa : std_logic_vector (53 downto 0);
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signal qb : std_logic_vector (53 downto 0);
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signal qc : std_logic_vector (53 downto 0);
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signal qd : std_logic_vector (53 downto 0);
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signal clock,rst,ena: std_logic;
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signal opcode,addcode:std_logic;
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signal dp0,dp1,cpx,cpy,cpz : std_logic_vector(31 downto 0);
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signal address: std_logic_vector (8 downto 0);
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signal opadd : std_logic_vector(1 downto 0);
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begin
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--! Generador de clock.
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clk_inst: clock_gen
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port map (clock,rst); -- Instanciacion simple.
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--! Device Under Test
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dude: raytrac
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generic map ("YES","YES") -- Test bench y Entrada registrada, pues la ROM no tiene salida registrada.
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port map(qa,qb,qc,qd,opadd(1),opadd(0),clock,rst,ena,cpx,cpy,cpz,dp0,dp1);
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--! Procedimiento para escribir los resultados del testbench
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sampleproc: process
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variable buff : line;
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file rombuff : text open write_mode is "TRACE_rom_content.csv";
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variable stop : integer := 0;
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begin
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write(buff,string'("#ROM memories test benching"));
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writeline(rombuff, buff);
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write(buff,string'("#{Time} {AddressR} {Opc Adc} {Ax,Ay,Az} {Bx,By,Bz} {Cx,Cy,Cz} {Dx,Dy,Dz}"));
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writeline(rombuff, buff);
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wait for 5 ns;
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wait until rst=not(rstMasterValue);
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wait until clock='1';
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wait for tclk2+tclk4; --! Garantizar la estabilidad de los datos que se van a observar en la salida.
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displayRom:
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loop
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write (buff,string'("{"));
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write (buff,now,unit =>ns);
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write (buff,string'("}{"));
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hexwrite_0 (buff,address(8 downto 0));
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write (buff,string'("}{"));
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hexwrite_0 (buff,opadd);
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write (buff,string'("} { "));
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hexwrite_0 (buff,qa(17 downto 0));
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write (buff,string'(","));
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hexwrite_0 (buff,qa(35 downto 18));
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write (buff,string'(","));
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hexwrite_0 (buff,qa(53 downto 36));
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write (buff,string'(" } "));
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write (buff,string'(" { "));
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hexwrite_0 (buff,qb(17 downto 0));
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write (buff,string'(","));
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hexwrite_0 (buff,qb(35 downto 18));
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write (buff,string'(","));
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hexwrite_0 (buff,qb(53 downto 36));
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write (buff,string'(" } "));
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write (buff,string'(" { "));
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hexwrite_0 (buff,qc(17 downto 0));
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write (buff,string'(","));
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hexwrite_0 (buff,qc(35 downto 18));
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write (buff,string'(","));
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hexwrite_0 (buff,qc(53 downto 36));
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write (buff,string'(" } "));
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write (buff,string'(" { "));
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hexwrite_0 (buff,qd(17 downto 0));
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write (buff,string'(","));
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hexwrite_0 (buff,qd(35 downto 18));
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write (buff,string'(","));
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hexwrite_0 (buff,qd(53 downto 36));
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write (buff,string'(" } "));
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writeline(rombuff,buff);
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wait for tclk;
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-- STOP FORREST!
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if opadd=X"2" and address=X"00" then
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if stop=1 then
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wait;
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else
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stop:=1;
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end if;
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end if;
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end loop displayRom;
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end process sampleproc;
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--! Descripcion del test: 512 x (2/clock) productos punto y 1024 x (1/clock) productos cruz.
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thetest:
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process (clock,rst)
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variable buff : line;
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file rombuff : text open write_mode is "TRACE_state_content";
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variable tbs : tbState;
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begin
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if rst=rstMasterValue then
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opcode <= '0';
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addcode <= '1';
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tbs := abcd;
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ena <= '1';
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address <= (others => '0');
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elsif clock'event and clock = '1' then
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opadd <= opcode & addcode;
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case tbs is
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when abcd =>
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if address = X"1FF" then
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write (buff,now,unit => ns);
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write (buff,string'(" S: abcd => axb"));
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writeline (rombuff,buff);
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tbs := axb;
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opcode <= '1';
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addcode <= not(addcode);
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end if;
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address <= address + 1;
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when axb =>
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write (buff,now,unit => ns);
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write (buff,string'(" S: axb => cxd"));
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writeline (rombuff,buff);
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tbs := cxd;
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addcode <= not(addcode);
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when cxd =>
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addcode <= not(addcode);
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if address=X"1FF" then
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write (buff,now,unit => ns);
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write (buff,string'(" S: cxd => stop"));
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writeline (rombuff,buff);
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tbs := stop;
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else
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write (buff,now,unit => ns);
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write (buff,string'(" S: cxd => axb"));
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writeline (rombuff,buff);
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tbs := axb;
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end if;
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address <= address + 1;
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when others =>
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null;
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end case;
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end if;
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end process thetest;
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--! 512x18 rom con los componentes ax.
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AX : altsyncram
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generic map (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => "memax.mif",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 512,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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ram_block_type => "M9K",
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widthad_a => 9,
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width_a => 18,
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width_byteena_a => 1
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)
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port map (
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clock0 => clock,
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address_a => address,
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q_a => qa (17 downto 0)
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);
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--! 512x18 rom con los componentes ay.
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AY : altsyncram
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generic map (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => ".\memay.mif",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 512,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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ram_block_type => "M9K",
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widthad_a => 9,
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width_a => 18,
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width_byteena_a => 1
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)
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port map (
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clock0 => clock,
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address_a => address,
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q_a => qa (35 downto 18)
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);
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--! 512x18 rom con los componentes az.
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AZ : altsyncram
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generic map (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => ".\memaz.mif",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 512,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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ram_block_type => "M9K",
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widthad_a => 9,
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width_a => 18,
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width_byteena_a => 1
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)
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port map (
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clock0 => clock,
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address_a => address,
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q_a => qa (53 downto 36)
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);
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--! 512x18 rom con los componentes bx.
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BX : altsyncram
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generic map (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => ".\membx.mif",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 512,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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ram_block_type => "M9K",
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widthad_a => 9,
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width_a => 18,
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width_byteena_a => 1
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)
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port map (
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clock0 => clock,
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address_a => address,
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q_a => qb (17 downto 0)
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);
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--! 512x18 rom con los componentes by.
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BY : altsyncram
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generic map (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => ".\memby.mif",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 512,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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ram_block_type => "M9K",
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widthad_a => 9,
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width_a => 18,
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width_byteena_a => 1
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)
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port map (
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clock0 => clock,
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address_a => address,
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q_a => qb (35 downto 18)
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);
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--! 512x18 rom con los componentes bz.
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BZ : altsyncram
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generic map (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => ".\membz.mif",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 512,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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ram_block_type => "M9K",
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widthad_a => 9,
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width_a => 18,
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width_byteena_a => 1
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)
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port map (
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clock0 => clock,
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address_a => address,
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q_a => qb (53 downto 36)
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);
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--! 512x18 rom con los componentes cx.
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CX : altsyncram
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generic map (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => ".\memcx.mif",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 512,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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ram_block_type => "M9K",
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widthad_a => 9,
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width_a => 18,
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width_byteena_a => 1
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)
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port map (
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clock0 => clock,
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address_a => address,
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q_a => qc (17 downto 0)
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);
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--! 512x18 rom con los componentes cy.
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CY : altsyncram
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generic map (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => ".\memcy.mif",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 512,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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ram_block_type => "M9K",
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widthad_a => 9,
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width_a => 18,
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width_byteena_a => 1
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)
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port map (
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clock0 => clock,
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address_a => address,
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q_a => qc (35 downto 18)
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);
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--! 512x18 rom con los componentes cz.
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CZ : altsyncram
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generic map (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => ".\memcz.mif",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 512,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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ram_block_type => "M9K",
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widthad_a => 9,
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width_a => 18,
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width_byteena_a => 1
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)
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port map (
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clock0 => clock,
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address_a => address,
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q_a => qc (53 downto 36)
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);
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--! 512x18 rom con los componentes dx.
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DX : altsyncram
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generic map (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => ".\memdx.mif",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 512,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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ram_block_type => "M9K",
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widthad_a => 9,
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width_a => 18,
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width_byteena_a => 1
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)
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port map (
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clock0 => clock,
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address_a => address,
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q_a => qd (17 downto 0)
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);
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--! 512x18 rom con los componentes dy.
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DY : altsyncram
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generic map (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => ".\memdy.mif",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 512,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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ram_block_type => "M9K",
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widthad_a => 9,
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width_a => 18,
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width_byteena_a => 1
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)
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port map (
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clock0 => clock,
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address_a => address,
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q_a => qd (35 downto 18)
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);
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--! 512x18 rom con los componentes dz.
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DZ : altsyncram
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generic map (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => ".\memdz.mif",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 512,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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ram_block_type => "M9K",
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widthad_a => 9,
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width_a => 18,
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width_byteena_a => 1
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)
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port map (
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clock0 => clock,
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address_a => address,
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q_a => qd (53 downto 36)
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);
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end tb_arch;
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No newline at end of file
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No newline at end of file
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