| Line 21... |
Line 21... |
use work.arithpack.all;
|
use work.arithpack.all;
|
|
|
entity uf is
|
entity uf is
|
port (
|
port (
|
opcode : in std_logic;
|
opcode : in std_logic;
|
m0f0,m0f1,m1f0m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0);
|
m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0);
|
cpx,cpy,cpz,dp0,dp1 : out std_logic_vector(31 downto 0);
|
cpx,cpy,cpz,dp0,dp1 : out std_logic_vector(31 downto 0);
|
clk,rst : in std_logic
|
clk,rst : in std_logic
|
);
|
);
|
end uf;
|
end uf;
|
|
|
| Line 33... |
Line 33... |
|
|
-- Stage 0 signals
|
-- Stage 0 signals
|
|
|
signal s0mf00,s0mf01,s0mf10,s0mf11,s0mf20,s0mf21,s0mf30,s0mf31,s0mf40,s0mf41,s0mf50,s0mf51 : std_logic_vector(17 downto 0);
|
signal s0mf00,s0mf01,s0mf10,s0mf11,s0mf20,s0mf21,s0mf30,s0mf31,s0mf40,s0mf41,s0mf50,s0mf51 : std_logic_vector(17 downto 0);
|
signal s0p0,s0p1, s0p2, s0p3, s0p4, s0p5 : std_logic_vector(31 downto 0);
|
signal s0p0,s0p1, s0p2, s0p3, s0p4, s0p5 : std_logic_vector(31 downto 0);
|
signal s0opcode;
|
signal s0opcode : std_logic;
|
|
|
--Stage 1 signals
|
--Stage 1 signals
|
|
|
signal s1p0, s1p1, s1p2, s1p3, s1p4, s1p5 : std_logic_vector (31 downto 0);
|
signal s1p0, s1p1, s1p2, s1p3, s1p4, s1p5 : std_logic_vector (31 downto 0);
|
signal s1a0, s1a1, s1a2 : std_logic_vector (31 downto 0);
|
signal s1a0, s1a1, s1a2 : std_logic_vector (31 downto 0);
|
signal s1opcode;
|
signal s1opcode : std_logic;
|
|
|
-- Some support signals
|
-- Some support signals
|
signal s1_internalCarry : std_logic_vector(2 downto 0);
|
signal s1_internalCarry : std_logic_vector(2 downto 0);
|
signal s2_internalCarry : std_logic_vector(1 downto 0);
|
signal s2_internalCarry : std_logic_vector(1 downto 0);
|
|
|
| Line 55... |
Line 55... |
|
|
begin
|
begin
|
|
|
-- Multiplicator Instantiation (StAgE 0)
|
-- Multiplicator Instantiation (StAgE 0)
|
|
|
m0 : r_a18_b18_smul_sc32_r
|
m0 : r_a18_b18_smul_c32_r
|
port map (
|
port map (
|
aclr => rst,
|
aclr => rst,
|
clock => clk,
|
clock => clk,
|
dataa => s0mf00,
|
dataa => s0mf00,
|
datab => s0mf01,
|
datab => s0mf01,
|
result => s0p0
|
result => s0p0
|
);
|
);
|
m1 : r_a18_b18_smul_sc32_r
|
m1 : r_a18_b18_smul_c32_r
|
port map (
|
port map (
|
aclr => rst,
|
aclr => rst,
|
clock => clk,
|
clock => clk,
|
dataa => s0mf10,
|
dataa => s0mf10,
|
datab => s0mf11,
|
datab => s0mf11,
|
result => s0p1
|
result => s0p1
|
);
|
);
|
m2 : r_a18_b18_smul_sc32_r
|
m2 : r_a18_b18_smul_c32_r
|
port map (
|
port map (
|
aclr => rst,
|
aclr => rst,
|
clock => clk,
|
clock => clk,
|
dataa => s0mf20,
|
dataa => s0mf20,
|
datab => s0mf21,
|
datab => s0mf21,
|
result => s0p2
|
result => s0p2
|
);
|
);
|
m3 : r_a18_b18_smul_sc32_r
|
m3 : r_a18_b18_smul_c32_r
|
port map (
|
port map (
|
aclr => rst,
|
aclr => rst,
|
clock => clk,
|
clock => clk,
|
dataa => s0mf30,
|
dataa => s0mf30,
|
datab => s0mf31,
|
datab => s0mf31,
|
result => s0p3
|
result => s0p3
|
);
|
);
|
m4 : r_a18_b18_smul_sc32_r
|
m4 : r_a18_b18_smul_c32_r
|
port map (
|
port map (
|
aclr => rst,
|
aclr => rst,
|
clock => clk,
|
clock => clk,
|
dataa => s0mf40,
|
dataa => s0mf40,
|
datab => s0mf41,
|
datab => s0mf41,
|
result => s0p4
|
result => s0p4
|
);
|
);
|
m5 : r_a18_b18_smul_sc32_r
|
m5 : r_a18_b18_smul_c32_r
|
port map (
|
port map (
|
aclr => rst,
|
aclr => rst,
|
clock => clk,
|
clock => clk,
|
dataa => s0mf50,
|
dataa => s0mf50,
|
datab => s0mf51,
|
datab => s0mf51,
|
| Line 109... |
Line 109... |
-- Adder Instantiation (sTaGe 1)
|
-- Adder Instantiation (sTaGe 1)
|
|
|
--Adder 0, low adder
|
--Adder 0, low adder
|
a0low : adder
|
a0low : adder
|
generic map (
|
generic map (
|
w => 16,
|
16,"CLA","YES" --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
--Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
subtractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
|
)
|
)
|
port map (
|
port map (
|
a => s1p0(15 downto 0),
|
a => s1p0(15 downto 0),
|
b => s1p1(15 downto 0),
|
b => s1p1(15 downto 0),
|
s => s1opcode,
|
s => s1opcode,
|
| Line 126... |
Line 125... |
--Adder 0, high adder
|
--Adder 0, high adder
|
a0high : adder
|
a0high : adder
|
generic map (
|
generic map (
|
w => 16,
|
w => 16,
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
subtractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
)
|
)
|
port map (
|
port map (
|
a => s1p0(31 downto 16),
|
a => s1p0(31 downto 16),
|
b => s1p1(31 downto 16),
|
b => s1p1(31 downto 16),
|
s => s1opcode,
|
s => s1opcode,
|
| Line 141... |
Line 140... |
--Adder 1, low adder
|
--Adder 1, low adder
|
a1low : adder
|
a1low : adder
|
generic map (
|
generic map (
|
w => 16,
|
w => 16,
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
subtractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
)
|
)
|
port map (
|
port map (
|
a => s1p2(15 downto 0),
|
a => s1p2(15 downto 0),
|
b => s1p3(15 downto 0),
|
b => s1p3(15 downto 0),
|
s => s1opcode,
|
s => s1opcode,
|
| Line 156... |
Line 155... |
--Adder 1, high adder
|
--Adder 1, high adder
|
a1high : adder
|
a1high : adder
|
generic map (
|
generic map (
|
w => 16,
|
w => 16,
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
subtractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
)
|
)
|
port map (
|
port map (
|
a => s1p2(31 downto 16),
|
a => s1p2(31 downto 16),
|
b => s1p3(31 downto 16),
|
b => s1p3(31 downto 16),
|
s => s1opcode,
|
s => s1opcode,
|
ci => s1_internalCarry(1),
|
ci => s1_internalCarry(1),
|
result => s1a1(31 downto 16),
|
result => s1a1(31 downto 16),
|
cout => open
|
cout => open
|
);
|
);
|
--Adder 2, low adder
|
--Adder 2, low adder
|
a1low : adder
|
a2low : adder
|
generic map (
|
generic map (
|
w => 16,
|
w => 16,
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
subtractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
)
|
)
|
port map (
|
port map (
|
a => s1p4(15 downto 0),
|
a => s1p4(15 downto 0),
|
b => s1p5(15 downto 0),
|
b => s1p5(15 downto 0),
|
s => s1opcode,
|
s => s1opcode,
|
ci => '0',
|
ci => '0',
|
result => s1a2(15 downto 0),
|
result => s1a2(15 downto 0),
|
cout => s1_internalCarry(2)
|
cout => s1_internalCarry(2)
|
);
|
);
|
--Adder 2, high adder
|
--Adder 2, high adder
|
a1high : adder
|
a2high : adder
|
generic map (
|
generic map (
|
w => 16,
|
w => 16,
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
subtractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
)
|
)
|
port map (
|
port map (
|
a => s1p4(31 downto 16),
|
a => s1p4(31 downto 16),
|
b => s1p5(31 downto 16),
|
b => s1p5(31 downto 16),
|
s => s1opcode,
|
s => s1opcode,
|
| Line 204... |
Line 203... |
--Adder 3, low adder
|
--Adder 3, low adder
|
a3low : adder
|
a3low : adder
|
generic map (
|
generic map (
|
w => 16,
|
w => 16,
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
subtractor_selector => "NO" --No Just Add.
|
substractor_selector => "NO" --No Just Add.
|
)
|
)
|
port map (
|
port map (
|
a => s2a0(15 downto 0),
|
a => s2a0(15 downto 0),
|
b => s2p2(15 downto 0),
|
b => s2p2(15 downto 0),
|
s => open,
|
s => '0',
|
ci => '0',
|
ci => '0',
|
result => s2a3(15 downto 0),
|
result => s2a3(15 downto 0),
|
cout => s2_internalCarry(0)
|
cout => s2_internalCarry(0)
|
);
|
);
|
--Adder 3, high adder
|
--Adder 3, high adder
|
a3high : adder
|
a3high : adder
|
generic map (
|
generic map (
|
w => 16,
|
w => 16,
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
subtractor_selector => "NO" --No Just Add.
|
substractor_selector => "NO" --No Just Add.
|
)
|
)
|
port map (
|
port map (
|
a => s2a0(31 downto 16),
|
a => s2a0(31 downto 16),
|
b => s2p2(31 downto 16),
|
b => s2p2(31 downto 16),
|
s => open,
|
s => '0',
|
ci => s2_internalCarry(0),
|
ci => s2_internalCarry(0),
|
result => s2a3(31 downto 16),
|
result => s2a3(31 downto 16),
|
cout => open
|
cout => open
|
);
|
);
|
--Adder 4, low adder
|
--Adder 4, low adder
|
a4low : adder
|
a4low : adder
|
generic map (
|
generic map (
|
w => 16,
|
w => 16,
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
subtractor_selector => "NO" --No Just Add.
|
substractor_selector => "NO" --No Just Add.
|
)
|
)
|
port map (
|
port map (
|
a => s2p3(15 downto 0),
|
a => s2p3(15 downto 0),
|
b => s2a2(15 downto 0),
|
b => s2a2(15 downto 0),
|
s => open,
|
s => '0',
|
ci => '0',
|
ci => '0',
|
result => s2a4(15 downto 0),
|
result => s2a4(15 downto 0),
|
cout => s2_internalCarry(1)
|
cout => s2_internalCarry(1)
|
);
|
);
|
--Adder 4, high adder
|
--Adder 4, high adder
|
a4high : adder
|
a4high : adder
|
generic map (
|
generic map (
|
w => 16,
|
w => 16,
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
subtractor_selector => "NO" --No Just Add.
|
substractor_selector => "NO" --No Just Add.
|
)
|
)
|
port map (
|
port map (
|
a => s2p3(31 downto 16),
|
a => s2p3(31 downto 16),
|
b => s2a2(31 downto 16),
|
b => s2a2(31 downto 16),
|
s => open,
|
s => '0',
|
ci => s2_internalCarry(1),
|
ci => s2_internalCarry(1),
|
result => s2a4(31 downto 16),
|
result => s2a4(31 downto 16),
|
cout => open
|
cout => open
|
);
|
);
|
|
|
| Line 296... |
Line 295... |
-- Looking into the design the stage 1 to stage 2 are the sequences pipe stages that must be controlled in this particular HDL.
|
-- Looking into the design the stage 1 to stage 2 are the sequences pipe stages that must be controlled in this particular HDL.
|
uf_seq: process (clk,rst)
|
uf_seq: process (clk,rst)
|
begin
|
begin
|
|
|
if rst=rstMasterValue then
|
if rst=rstMasterValue then
|
s0opcode <= (others => '0');
|
s0opcode <= '0';
|
s1opcode <= (others => '0');
|
s1opcode <= '0';
|
|
|
s2a2 <= (others => '0');
|
s2a2 <= (others => '0');
|
s2p3 <= (others => '0');
|
s2p3 <= (others => '0');
|
s2p2 <= (others => '0');
|
s2p2 <= (others => '0');
|
s2a0 <= (others => '0');
|
s2a0 <= (others => '0');
|
