| Line 31... |
Line 31... |
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architecture uf_arch of uf is
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architecture uf_arch of uf is
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-- Stage 0 signals
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-- Stage 0 signals
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signal s0mf00,s0mf01,s0mf10,s0mf11,s0mf20,s0mf21,s0mf30,s0mf31,s0mf40,s0mf41,s0mf50,s0mf51 : std_logic_vector(17 downto 0);
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signal stage0mf00,stage0mf01,stage0mf10,stage0mf11,stage0mf20,stage0mf21,stage0mf30,stage0mf31,stage0mf40,stage0mf41,stage0mf50,stage0mf51 : std_logic_vector(17 downto 0);
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signal s0p0,s0p1, s0p2, s0p3, s0p4, s0p5 : std_logic_vector(31 downto 0);
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signal stage0p0,stage0p1, stage0p2, stage0p3, stage0p4, stage0p5 : std_logic_vector(31 downto 0);
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signal s0opcode : std_logic;
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signal stage0opcode : std_logic;
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--Stage 1 signals
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--Stage 1 signals
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signal s1p0, s1p1, s1p2, s1p3, s1p4, s1p5 : std_logic_vector (31 downto 0);
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signal stage1p0, stage1p1, stage1p2, stage1p3, stage1p4, stage1p5 : std_logic_vector (31 downto 0);
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signal s1a0, s1a1, s1a2 : std_logic_vector (31 downto 0);
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signal stage1a0, stage1a1, stage1a2 : std_logic_vector (31 downto 0);
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signal s1opcode : std_logic;
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signal stage1opcode : std_logic;
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-- Some support signals
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-- Some support signals
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signal s1_internalCarry : std_logic_vector(2 downto 0);
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signal stage1_internalCarry : std_logic_vector(2 downto 0);
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signal s2_internalCarry : std_logic_vector(1 downto 0);
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signal stage2_internalCarry : std_logic_vector(1 downto 0);
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--Stage 2 signals
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--Stage 2 signals
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signal s2a0, s2a2, s2a3, s2a4, s2p2, s2p3 : std_logic_vector (31 downto 0);
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signal stage2a0, stage2a2, stage2a3, stage2a4, stage2p2, stage2p3 : std_logic_vector (31 downto 0);
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begin
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begin
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| Line 59... |
Line 59... |
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m0 : r_a18_b18_smul_c32_r
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m0 : r_a18_b18_smul_c32_r
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => s0mf00,
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dataa => stage0mf00,
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datab => s0mf01,
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datab => stage0mf01,
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result => s0p0
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result => stage0p0
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);
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);
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m1 : r_a18_b18_smul_c32_r
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m1 : r_a18_b18_smul_c32_r
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => s0mf10,
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dataa => stage0mf10,
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datab => s0mf11,
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datab => stage0mf11,
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result => s0p1
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result => stage0p1
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);
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);
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m2 : r_a18_b18_smul_c32_r
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m2 : r_a18_b18_smul_c32_r
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => s0mf20,
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dataa => stage0mf20,
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datab => s0mf21,
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datab => stage0mf21,
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result => s0p2
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result => stage0p2
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);
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);
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m3 : r_a18_b18_smul_c32_r
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m3 : r_a18_b18_smul_c32_r
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => s0mf30,
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dataa => stage0mf30,
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datab => s0mf31,
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datab => stage0mf31,
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result => s0p3
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result => stage0p3
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);
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);
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m4 : r_a18_b18_smul_c32_r
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m4 : r_a18_b18_smul_c32_r
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => s0mf40,
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dataa => stage0mf40,
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datab => s0mf41,
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datab => stage0mf41,
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result => s0p4
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result => stage0p4
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);
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);
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m5 : r_a18_b18_smul_c32_r
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m5 : r_a18_b18_smul_c32_r
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => s0mf50,
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dataa => stage0mf50,
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datab => s0mf51,
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datab => stage0mf51,
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result => s0p5
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result => stage0p5
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);
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);
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-- Adder Instantiation (sTaGe 1)
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-- Adder Instantiation (sTaGe 1)
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--Adder 0, low adder
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--Adder 0, low adder
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| Line 113... |
Line 113... |
generic map (
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generic map (
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16,"CLA","YES" --Carry Look Ahead Logic (More Gates Used, But Less Time)
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16,"CLA","YES" --Carry Look Ahead Logic (More Gates Used, But Less Time)
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--Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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--Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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)
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)
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port map (
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port map (
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a => s1p0(15 downto 0),
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a => stage1p0(15 downto 0),
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b => s1p1(15 downto 0),
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b => stage1p1(15 downto 0),
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s => s1opcode,
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s => stage1opcode,
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ci => '0',
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ci => '0',
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result => s1a0(15 downto 0),
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result => stage1a0(15 downto 0),
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cout => s1_internalCarry(0)
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cout => stage1_internalCarry(0)
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);
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);
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--Adder 0, high adder
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--Adder 0, high adder
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a0high : adder
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a0high : adder
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generic map (
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generic map (
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w => 16,
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w => 16,
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carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
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carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
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substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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)
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)
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port map (
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port map (
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a => s1p0(31 downto 16),
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a => stage1p0(31 downto 16),
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b => s1p1(31 downto 16),
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b => stage1p1(31 downto 16),
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s => s1opcode,
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s => stage1opcode,
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ci => s1_internalCarry(0),
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ci => stage1_internalCarry(0),
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result => s1a0(31 downto 16),
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result => stage1a0(31 downto 16),
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cout => open
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cout => open
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);
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);
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--Adder 1, low adder
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--Adder 1, low adder
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a1low : adder
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a1low : adder
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generic map (
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generic map (
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w => 16,
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w => 16,
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carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
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carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
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substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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)
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)
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port map (
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port map (
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a => s1p2(15 downto 0),
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a => stage1p2(15 downto 0),
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b => s1p3(15 downto 0),
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b => stage1p3(15 downto 0),
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s => s1opcode,
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s => stage1opcode,
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ci => '0',
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ci => '0',
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result => s1a1(15 downto 0),
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result => stage1a1(15 downto 0),
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cout => s1_internalCarry(1)
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cout => stage1_internalCarry(1)
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);
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);
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--Adder 1, high adder
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--Adder 1, high adder
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a1high : adder
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a1high : adder
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generic map (
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generic map (
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w => 16,
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w => 16,
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
)
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)
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port map (
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port map (
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a => s1p2(31 downto 16),
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a => stage1p2(31 downto 16),
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b => s1p3(31 downto 16),
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b => stage1p3(31 downto 16),
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s => s1opcode,
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s => stage1opcode,
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ci => s1_internalCarry(1),
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ci => stage1_internalCarry(1),
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result => s1a1(31 downto 16),
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result => stage1a1(31 downto 16),
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cout => open
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cout => open
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);
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);
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--Adder 2, low adder
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--Adder 2, low adder
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a2low : adder
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a2low : adder
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generic map (
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generic map (
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w => 16,
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w => 16,
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carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
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carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
)
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)
|
port map (
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port map (
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a => s1p4(15 downto 0),
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a => stage1p4(15 downto 0),
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b => s1p5(15 downto 0),
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b => stage1p5(15 downto 0),
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s => s1opcode,
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s => stage1opcode,
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ci => '0',
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ci => '0',
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result => s1a2(15 downto 0),
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result => stage1a2(15 downto 0),
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cout => s1_internalCarry(2)
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cout => stage1_internalCarry(2)
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);
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);
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--Adder 2, high adder
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--Adder 2, high adder
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a2high : adder
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a2high : adder
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generic map (
|
generic map (
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w => 16,
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w => 16,
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
|
)
|
)
|
port map (
|
port map (
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a => s1p4(31 downto 16),
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a => stage1p4(31 downto 16),
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b => s1p5(31 downto 16),
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b => stage1p5(31 downto 16),
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s => s1opcode,
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s => stage1opcode,
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ci => s1_internalCarry(2),
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ci => stage1_internalCarry(2),
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result => s1a2(31 downto 16),
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result => stage1a2(31 downto 16),
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cout => open
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cout => open
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);
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);
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-- Adder Instantiation (Stage 2)
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-- Adder Instantiation (Stage 2)
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| Line 206... |
Line 206... |
w => 16,
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w => 16,
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carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
substractor_selector => "NO" --No Just Add.
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substractor_selector => "NO" --No Just Add.
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)
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)
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port map (
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port map (
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a => s2a0(15 downto 0),
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a => stage2a0(15 downto 0),
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b => s2p2(15 downto 0),
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b => stage2p2(15 downto 0),
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s => '0',
|
s => '0',
|
ci => '0',
|
ci => '0',
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result => s2a3(15 downto 0),
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result => stage2a3(15 downto 0),
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cout => s2_internalCarry(0)
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cout => stage2_internalCarry(0)
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);
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);
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--Adder 3, high adder
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--Adder 3, high adder
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a3high : adder
|
a3high : adder
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generic map (
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generic map (
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w => 16,
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w => 16,
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carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
substractor_selector => "NO" --No Just Add.
|
substractor_selector => "NO" --No Just Add.
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)
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)
|
port map (
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port map (
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a => s2a0(31 downto 16),
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a => stage2a0(31 downto 16),
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b => s2p2(31 downto 16),
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b => stage2p2(31 downto 16),
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s => '0',
|
s => '0',
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ci => s2_internalCarry(0),
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ci => stage2_internalCarry(0),
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result => s2a3(31 downto 16),
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result => stage2a3(31 downto 16),
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cout => open
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cout => open
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);
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);
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--Adder 4, low adder
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--Adder 4, low adder
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a4low : adder
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a4low : adder
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generic map (
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generic map (
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w => 16,
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w => 16,
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carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
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carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
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substractor_selector => "NO" --No Just Add.
|
substractor_selector => "NO" --No Just Add.
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)
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)
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port map (
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port map (
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a => s2p3(15 downto 0),
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a => stage2p3(15 downto 0),
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b => s2a2(15 downto 0),
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b => stage2a2(15 downto 0),
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s => '0',
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s => '0',
|
ci => '0',
|
ci => '0',
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result => s2a4(15 downto 0),
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result => stage2a4(15 downto 0),
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cout => s2_internalCarry(1)
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cout => stage2_internalCarry(1)
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);
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);
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--Adder 4, high adder
|
--Adder 4, high adder
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a4high : adder
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a4high : adder
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generic map (
|
generic map (
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w => 16,
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w => 16,
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)
|
substractor_selector => "NO" --No Just Add.
|
substractor_selector => "NO" --No Just Add.
|
)
|
)
|
port map (
|
port map (
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a => s2p3(31 downto 16),
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a => stage2p3(31 downto 16),
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b => s2a2(31 downto 16),
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b => stage2a2(31 downto 16),
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s => '0',
|
s => '0',
|
ci => s2_internalCarry(1),
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ci => stage2_internalCarry(1),
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result => s2a4(31 downto 16),
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result => stage2a4(31 downto 16),
|
cout => open
|
cout => open
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);
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);
|
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-- Incoming from opcoder.vhd signals into pipeline's stage 0.
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-- Incoming from opcoder.vhd signals into pipeline's stage 0.
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s0mf00 <= m0f0;
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stage0mf00 <= m0f0;
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s0mf01 <= m0f1;
|
stage0mf01 <= m0f1;
|
s0mf10 <= m1f0;
|
stage0mf10 <= m1f0;
|
s0mf11 <= m1f1;
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stage0mf11 <= m1f1;
|
s0mf20 <= m2f0;
|
stage0mf20 <= m2f0;
|
s0mf21 <= m2f1;
|
stage0mf21 <= m2f1;
|
s0mf30 <= m3f0;
|
stage0mf30 <= m3f0;
|
s0mf31 <= m3f1;
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stage0mf31 <= m3f1;
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s0mf40 <= m4f0;
|
stage0mf40 <= m4f0;
|
s0mf41 <= m4f1;
|
stage0mf41 <= m4f1;
|
s0mf50 <= m5f0;
|
stage0mf50 <= m5f0;
|
s0mf51 <= m5f1;
|
stage0mf51 <= m5f1;
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|
|
-- Signal sequencing: as the multipliers use registered output and registered input is not necessary to write the sequence of stage 0 signals to stage 1 signals.
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-- Signal sequencing: as the multipliers use registered output and registered input is not necessary to write the sequence of stage 0 signals to stage 1 signals.
|
-- so the simplistic path is taken: simply connect stage 0 to stage 1 lines. However this would not apply for the opcode signal
|
-- so the simplistic path is taken: simply connect stage 0 to stage 1 lines. However this would not apply for the opcode signal
|
s1p0 <= s0p0;
|
stage1p0 <= stage0p0;
|
s1p1 <= s0p1;
|
stage1p1 <= stage0p1;
|
s1p2 <= s0p2;
|
stage1p2 <= stage0p2;
|
s1p3 <= s0p3;
|
stage1p3 <= stage0p3;
|
s1p4 <= s0p4;
|
stage1p4 <= stage0p4;
|
s1p5 <= s0p5;
|
stage1p5 <= stage0p5;
|
|
|
|
|
--Outcoming to the rest of the system (by the time i wrote this i dont know where this leads to... jeje)
|
--Outcoming to the rest of the system (by the time i wrote this i dont know where this leads to... jeje)
|
cpx <= s1a0;
|
cpx <= stage1a0;
|
cpy <= s1a1;
|
cpy <= stage1a1;
|
cpz <= s1a2;
|
cpz <= stage1a2;
|
dp0 <= s2a3;
|
dp0 <= stage2a3;
|
dp1 <= s2a4;
|
dp1 <= stage2a4;
|
|
|
-- Looking into the design the stage 1 to stage 2 are the sequences pipe stages that must be controlled in this particular HDL.
|
-- Looking into the design the stage 1 to stage 2 are the sequences pipe stages that must be controlled in this particular HDL.
|
uf_seq: process (clk,rst)
|
uf_seq: process (clk,rst,opcode)
|
begin
|
begin
|
|
|
if rst=rstMasterValue then
|
if rst=rstMasterValue then
|
s0opcode <= '0';
|
stage0opcode <= '0';
|
s1opcode <= '0';
|
stage1opcode <= '0';
|
|
|
s2a2 <= (others => '0');
|
stage2a2 <= (others => '0');
|
s2p3 <= (others => '0');
|
stage2p3 <= (others => '0');
|
s2p2 <= (others => '0');
|
stage2p2 <= (others => '0');
|
s2a0 <= (others => '0');
|
stage2a0 <= (others => '0');
|
|
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
|
|
s2a2 <= s1a2;
|
stage2a2 <= stage1a2;
|
s2p3 <= s1p3;
|
stage2p3 <= stage1p3;
|
s2p2 <= s1p2;
|
stage2p2 <= stage1p2;
|
s2a0 <= s1a0;
|
stage2a0 <= stage1a0;
|
|
|
-- Opcode control sequence
|
-- Opcode control sequence
|
s0opcode <= opcode;
|
stage0opcode <= opcode;
|
s1opcode <= s0opcode;
|
stage1opcode <= stage0opcode;
|
|
|
end if;
|
end if;
|
end process uf_seq;
|
end process uf_seq;
|
|
uf_seq2: process (clk,rst,stage0opcode)
|
|
begin
|
|
|
|
if rst=rstMasterValue then
|
|
|
|
|
|
elsif clk'event and clk='1' then
|
|
|
|
|
|
end if;
|
|
|
|
end process uf_seq2;
|
|
|
|
|
|
|
end uf_arch;
|
end uf_arch;
|
|
|
No newline at end of file
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No newline at end of file
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