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--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
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--! Libreria de definicion de senales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n Signal and types definition library. This library also defines
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library ieee;
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library ieee;
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--! Paquete de definicion estandard de logica. Standard logic definition pack.
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--! Paquete de definicion estandard de logica. Standard logic definition pack.
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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--! Paquete para el manejo de aritmŽtica con signo sobre el tipo std_logic_vector
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use ieee.std_logic_signed.all;
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--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
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--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
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use work.arithpack.all;
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use work.arithpack.all;
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--! uf es la descripción del circuito que realiza la aritmética del Rt Engine.
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--! uf es la descripción del circuito que realiza la aritmética del Rt Engine.
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Line 38... |
--! Esta entidad utiliza las señales de control clk y rst.}
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--! Esta entidad utiliza las señales de control clk y rst.}
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--! \n\n
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--! \n\n
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--! La característica fundamental de uf, es que puede realizar 2 operaciones de producto punto al mimso tiempo ó una operación de producto cruz al mismo tiempo. La otra característica importante es que el pipe de producto punto es mas largo que el pipe de producto cruz: el producto punto tomará 3 clocks para realizarse, mientras que el procto punto tomara 4 clocks para realizarse.
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--! La característica fundamental de uf, es que puede realizar 2 operaciones de producto punto al mimso tiempo ó una operación de producto cruz al mismo tiempo. La otra característica importante es que el pipe de producto punto es mas largo que el pipe de producto cruz: el producto punto tomará 3 clocks para realizarse, mientras que el procto punto tomara 4 clocks para realizarse.
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entity uf is
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entity uf is
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generic (
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use_std_logic_signed : string := "YES"
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);
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port (
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port (
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opcode : in std_logic; --! Entrada que dentro de la arquitectura funciona como selector de la operación que se lleva a cabo en la primera etapa de sumadores/restadores.
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opcode : in std_logic; --! Entrada que dentro de la arquitectura funciona como selector de la operación que se lleva a cabo en la primera etapa de sumadores/restadores.
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0); --! Entradas que van conectadas a los multiplicadores en la primera etapa de la descripción.
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0); --! Entradas que van conectadas a los multiplicadores en la primera etapa de la descripción.
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cpx,cpy,cpz,dp0,dp1 : out std_logic_vector(31 downto 0); --! Salidas donde se registran los resultados de las operaciones aritméticas: cpx,cpy,cpz serán los componentes del vector que da por resultado el producto cruz entre los vectores AxB ó CxD.
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cpx,cpy,cpz,dp0,dp1 : out std_logic_vector(31 downto 0); --! Salidas donde se registran los resultados de las operaciones aritméticas: cpx,cpy,cpz serán los componentes del vector que da por resultado el producto cruz entre los vectores AxB ó CxD.
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clk,rst : in std_logic --! Las entradas de control usuales.
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clk,rst : in std_logic --! Las entradas de control usuales.
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Line 135... |
dataa => stage0mf50,
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dataa => stage0mf50,
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datab => stage0mf51,
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datab => stage0mf51,
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result => stage0p5
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result => stage0p5
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);
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);
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useIeee:
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if use_std_logic_signed="YES" generate
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-- Adder Instantiation (sTaGe 1)
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-- Adder Instantiation (sTaGe 1)
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stage1adderProc:
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process (stage1p0,stage1p1,stage1p2,stage1p3,stage1p4,stage1p5,stage1opcode)
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begin
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case (stage1opcode) is
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when '1' => -- Cross Product
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stage1a0 <= stage1p0-stage1p1;
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stage1a2 <= stage1p4-stage1p5;
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when others => -- Dot Product
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stage1a0 <= stage1p0+stage1p1;
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stage1a2 <= stage1p4+stage1p5;
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end case;
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end process stage1adderProc;
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stage1a1 <= stage1p2-stage1p3; -- This is always going to be a substraction
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-- Adder Instantiation (Stage 2)
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stage2a3 <= stage2a0+stage2p2;
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stage2a4 <= stage2p3+stage2a2;
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end generate useIeee;
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dontUseIeee:
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if use_std_logic_signed="NO" generate
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--! Adder 0, 16 bit carry lookahead low adder.
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--! Adder 0, 16 bit carry lookahead low adder.
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a0low : adder
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a0low : adder
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generic map (
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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16,"CLA","YES" -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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)
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port map (stage1p0(15 downto 0),stage1p1(15 downto 0),stage1opcode,'0',stage1a0(15 downto 0),stage1_internalCarry(0));
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port map (
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a => stage1p0(15 downto 0),
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b => stage1p1(15 downto 0),
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s => stage1opcode,
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ci => '0',
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result => stage1a0(15 downto 0),
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cout => stage1_internalCarry(0)
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);
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--Adder 0, 16 bit carry lookahead high adder.
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--Adder 0, 16 bit carry lookahead high adder.
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a0high : adder
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a0high : adder
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generic map (
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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w => 16,
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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port map (stage1p0(31 downto 16),stage1p1(31 downto 16),stage1opcode,stage1_internalCarry(0),stage1a0(31 downto 16),open);
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substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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)
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port map (
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a => stage1p0(31 downto 16),
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b => stage1p1(31 downto 16),
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s => stage1opcode,
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ci => stage1_internalCarry(0),
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result => stage1a0(31 downto 16),
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cout => open
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);
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--! Adder 1, 16 bit carry lookahead low adder.
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--! Adder 1, 16 bit carry lookahead low adder.
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a1low : adder
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a1low : adder
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generic map (
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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w => 16,
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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port map (stage1p2(15 downto 0),stage1p3(15 downto 0),'1','0',stage1a1(15 downto 0),stage1_internalCarry(1));
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substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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)
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port map (
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a => stage1p2(15 downto 0),
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b => stage1p3(15 downto 0),
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s => stage1opcode,
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ci => '0',
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result => stage1a1(15 downto 0),
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cout => stage1_internalCarry(1)
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);
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--! Adder 1, 16 bit carry lookahead high adder.
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--! Adder 1, 16 bit carry lookahead high adder.
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a1high : adder
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a1high : adder
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generic map (
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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w => 16,
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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port map (stage1p2(31 downto 16),stage1p3(31 downto 16),'1',stage1_internalCarry(1),stage1a1(31 downto 16),open);
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substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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)
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port map (
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a => stage1p2(31 downto 16),
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b => stage1p3(31 downto 16),
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s => stage1opcode,
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ci => stage1_internalCarry(1),
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result => stage1a1(31 downto 16),
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cout => open
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);
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--! Adder 2, 16 bit carry lookahead low adder.
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--! Adder 2, 16 bit carry lookahead low adder.
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a2low : adder
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a2low : adder
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generic map (
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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w => 16,
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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port map (stage1p4(15 downto 0),stage1p5(15 downto 0),stage1opcode,'0',stage1a2(15 downto 0),stage1_internalCarry(2));
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substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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)
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port map (
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a => stage1p4(15 downto 0),
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b => stage1p5(15 downto 0),
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s => stage1opcode,
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ci => '0',
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result => stage1a2(15 downto 0),
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cout => stage1_internalCarry(2)
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);
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--! Adder 2, 16 bit carry lookahead high adder.
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--! Adder 2, 16 bit carry lookahead high adder.
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a2high : adder
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a2high : adder
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generic map (
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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w => 16,
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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port map (stage1p4(31 downto 16),stage1p5(31 downto 16),stage1opcode,stage1_internalCarry(2),stage1a2(31 downto 16),open);
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substractor_selector => "YES" -- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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)
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port map (
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a => stage1p4(31 downto 16),
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b => stage1p5(31 downto 16),
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s => stage1opcode,
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ci => stage1_internalCarry(2),
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result => stage1a2(31 downto 16),
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cout => open
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);
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-- Adder Instantiation (Stage 2)
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-- Adder Instantiation (Stage 2)
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--! Adder 3, 16 bit carry lookahead low adder.
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--! Adder 3, 16 bit carry lookahead low adder.
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a3low : adder
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a3low : adder
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generic map (
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generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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w => 16,
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-- Dont instantiate Xor gates stage in the adder.
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carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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port map (stage2a0(15 downto 0),stage2p2(15 downto 0),'0','0',stage2a3(15 downto 0),stage2_internalCarry(0));
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substractor_selector => "NO" -- No Just Add.
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)
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port map (
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a => stage2a0(15 downto 0),
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b => stage2p2(15 downto 0),
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s => '0',
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ci => '0',
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result => stage2a3(15 downto 0),
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cout => stage2_internalCarry(0)
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);
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--Adder 3, 16 bit carry lookahead high adder.
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--Adder 3, 16 bit carry lookahead high adder.
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a3high : adder
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a3high : adder
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generic map (
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generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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w => 16,
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-- Dont instantiate Xor gates stage in the adder.
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carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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port map (stage2a0(31 downto 16),stage2p2(31 downto 16),'0',stage2_internalCarry(0),stage2a3(31 downto 16),open);
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substractor_selector => "NO" -- No Just Add.
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)
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port map (
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a => stage2a0(31 downto 16),
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b => stage2p2(31 downto 16),
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s => '0',
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ci => stage2_internalCarry(0),
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result => stage2a3(31 downto 16),
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cout => open
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);
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--! Adder 4, 16 bit carry lookahead low adder.
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--! Adder 4, 16 bit carry lookahead low adder.
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a4low : adder
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a4low : adder
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generic map (
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generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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w => 16,
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-- Dont instantiate Xor gates stage in the adder.
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carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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port map (stage2p3(15 downto 0),stage2a2(15 downto 0),'0','0',stage2a4(15 downto 0),stage2_internalCarry(1));
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substractor_selector => "NO" -- No Just Add.
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)
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port map (
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a => stage2p3(15 downto 0),
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b => stage2a2(15 downto 0),
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s => '0',
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ci => '0',
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result => stage2a4(15 downto 0),
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cout => stage2_internalCarry(1)
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);
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--! Adder 4, 16 bit carry lookahead high adder.
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--! Adder 4, 16 bit carry lookahead high adder.
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a4high : adder
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a4high : adder
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generic map (
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generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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w => 16,
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-- Dont instantiate Xor gates stage in the adder.
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carry_logic => "CLA", -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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port map (stage2p3(31 downto 16),stage2a2(31 downto 16),'0',stage2_internalCarry(1),stage2a4(31 downto 16),open);
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substractor_selector => "NO" -- No Just Add.
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)
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port map (
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a => stage2p3(31 downto 16),
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b => stage2a2(31 downto 16),
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s => '0',
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ci => stage2_internalCarry(1),
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result => stage2a4(31 downto 16),
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cout => open
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);
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end generate dontUseIeee;
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-- Incoming from opcoder.vhd signals into pipeline's stage 0.
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-- Incoming from opcoder.vhd signals into pipeline's stage 0.
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stage0mf00 <= m0f0;
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stage0mf00 <= m0f0;
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stage0mf01 <= m0f1;
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stage0mf01 <= m0f1;
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stage0mf10 <= m1f0;
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stage0mf10 <= m1f0;
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stage0mf11 <= m1f1;
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stage0mf11 <= m1f1;
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