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Line 39... |
--! \n\n
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--! \n\n
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--! La característica fundamental de uf, es que puede realizar 2 operaciones de producto punto al mimso tiempo ó una operación de producto cruz al mismo tiempo. La otra característica importante es que el pipe de producto punto es mas largo que el pipe de producto cruz: el producto punto tomará 3 clocks para realizarse, mientras que el procto punto tomara 4 clocks para realizarse.
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--! La característica fundamental de uf, es que puede realizar 2 operaciones de producto punto al mimso tiempo ó una operación de producto cruz al mismo tiempo. La otra característica importante es que el pipe de producto punto es mas largo que el pipe de producto cruz: el producto punto tomará 3 clocks para realizarse, mientras que el procto punto tomara 4 clocks para realizarse.
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entity uf is
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entity uf is
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generic (
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generic (
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use_std_logic_signed : string := "NO"
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use_std_logic_signed : string := "NO";
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carry_logic : string := "CLA"
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);
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);
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port (
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port (
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opcode : in std_logic; --! Entrada que dentro de la arquitectura funciona como selector de la operación que se lleva a cabo en la primera etapa de sumadores/restadores.
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opcode : in std_logic; --! Entrada que dentro de la arquitectura funciona como selector de la operación que se lleva a cabo en la primera etapa de sumadores/restadores.
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0); --! Entradas que van conectadas a los multiplicadores en la primera etapa de la descripción.
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0); --! Entradas que van conectadas a los multiplicadores en la primera etapa de la descripción.
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cpx,cpy,cpz,dp0,dp1 : out std_logic_vector(31 downto 0); --! Salidas donde se registran los resultados de las operaciones aritméticas: cpx,cpy,cpz serán los componentes del vector que da por resultado el producto cruz entre los vectores AxB ó CxD.
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cpx,cpy,cpz,dp0,dp1 : out std_logic_vector(31 downto 0); --! Salidas donde se registran los resultados de las operaciones aritméticas: cpx,cpy,cpz serán los componentes del vector que da por resultado el producto cruz entre los vectores AxB ó CxD.
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| Line 162... |
Line 163... |
end generate useIeee;
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end generate useIeee;
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dontUseIeee:
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dontUseIeee:
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if use_std_logic_signed="NO" generate
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if use_std_logic_signed="NO" generate
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--! Adder 0, 16 bit carry lookahead low adder.
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--! Adder 0, 16 bit carry lookahead low adder.
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a0low : adder
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a0low : adder
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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port map (stage1p0(15 downto 0),stage1p1(15 downto 0),stageSRopcode,'0',stage1a0(15 downto 0),stage1_internalCarry(0));
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port map (stage1p0(15 downto 0),stage1p1(15 downto 0),stageSRopcode,'0',stage1a0(15 downto 0),stage1_internalCarry(0));
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--Adder 0, 16 bit carry lookahead high adder.
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--Adder 0, 16 bit carry lookahead high adder.
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a0high : adder
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a0high : adder
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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port map (stage1p0(31 downto 16),stage1p1(31 downto 16),stageSRopcode,stage1_internalCarry(0),stage1a0(31 downto 16),open);
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port map (stage1p0(31 downto 16),stage1p1(31 downto 16),stageSRopcode,stage1_internalCarry(0),stage1a0(31 downto 16),open);
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--! Adder 1, 16 bit carry lookahead low adder.
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--! Adder 1, 16 bit carry lookahead low adder.
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a1low : adder
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a1low : adder
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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port map (stage1p2(15 downto 0),stage1p3(15 downto 0),'1','0',stage1a1(15 downto 0),stage1_internalCarry(1));
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port map (stage1p2(15 downto 0),stage1p3(15 downto 0),'1','0',stage1a1(15 downto 0),stage1_internalCarry(1));
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--! Adder 1, 16 bit carry lookahead high adder.
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--! Adder 1, 16 bit carry lookahead high adder.
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a1high : adder
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a1high : adder
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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port map (stage1p2(31 downto 16),stage1p3(31 downto 16),'1',stage1_internalCarry(1),stage1a1(31 downto 16),open);
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port map (stage1p2(31 downto 16),stage1p3(31 downto 16),'1',stage1_internalCarry(1),stage1a1(31 downto 16),open);
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--! Adder 2, 16 bit carry lookahead low adder.
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--! Adder 2, 16 bit carry lookahead low adder.
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a2low : adder
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a2low : adder
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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port map (stage1p4(15 downto 0),stage1p5(15 downto 0),stageSRopcode,'0',stage1a2(15 downto 0),stage1_internalCarry(2));
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port map (stage1p4(15 downto 0),stage1p5(15 downto 0),stageSRopcode,'0',stage1a2(15 downto 0),stage1_internalCarry(2));
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--! Adder 2, 16 bit carry lookahead high adder.
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--! Adder 2, 16 bit carry lookahead high adder.
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a2high : adder
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a2high : adder
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generic map (16,"CLA","YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"YES") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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-- Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
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port map (stage1p4(31 downto 16),stage1p5(31 downto 16),stageSRopcode,stage1_internalCarry(2),stage1a2(31 downto 16),open);
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port map (stage1p4(31 downto 16),stage1p5(31 downto 16),stageSRopcode,stage1_internalCarry(2),stage1a2(31 downto 16),open);
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-- Adder Instantiation (Stage 2)
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-- Adder Instantiation (Stage 2)
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--! Adder 3, 16 bit carry lookahead low adder.
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--! Adder 3, 16 bit carry lookahead low adder.
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a3low : adder
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a3low : adder
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generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Dont instantiate Xor gates stage in the adder.
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-- Dont instantiate Xor gates stage in the adder.
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port map (stage2a0(15 downto 0),stage2p2(15 downto 0),'0','0',stage2a3(15 downto 0),stage2_internalCarry(0));
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port map (stage2a0(15 downto 0),stage2p2(15 downto 0),'0','0',stage2a3(15 downto 0),stage2_internalCarry(0));
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--Adder 3, 16 bit carry lookahead high adder.
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--Adder 3, 16 bit carry lookahead high adder.
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a3high : adder
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a3high : adder
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generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Dont instantiate Xor gates stage in the adder.
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-- Dont instantiate Xor gates stage in the adder.
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port map (stage2a0(31 downto 16),stage2p2(31 downto 16),'0',stage2_internalCarry(0),stage2a3(31 downto 16),open);
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port map (stage2a0(31 downto 16),stage2p2(31 downto 16),'0',stage2_internalCarry(0),stage2a3(31 downto 16),open);
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--! Adder 4, 16 bit carry lookahead low adder.
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--! Adder 4, 16 bit carry lookahead low adder.
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a4low : adder
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a4low : adder
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generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Dont instantiate Xor gates stage in the adder.
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-- Dont instantiate Xor gates stage in the adder.
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port map (stage2p3(15 downto 0),stage2a2(15 downto 0),'0','0',stage2a4(15 downto 0),stage2_internalCarry(1));
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port map (stage2p3(15 downto 0),stage2a2(15 downto 0),'0','0',stage2a4(15 downto 0),stage2_internalCarry(1));
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--! Adder 4, 16 bit carry lookahead high adder.
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--! Adder 4, 16 bit carry lookahead high adder.
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a4high : adder
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a4high : adder
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generic map (16,"CLA","NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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generic map (16,carry_logic,"NO") -- Carry Look Ahead Logic (More Gates Used, But Less Time)
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-- Dont instantiate Xor gates stage in the adder.
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-- Dont instantiate Xor gates stage in the adder.
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port map (stage2p3(31 downto 16),stage2a2(31 downto 16),'0',stage2_internalCarry(1),stage2a4(31 downto 16),open);
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port map (stage2p3(31 downto 16),stage2a2(31 downto 16),'0',stage2_internalCarry(1),stage2a4(31 downto 16),open);
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end generate dontUseIeee;
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end generate dontUseIeee;
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-- Incoming from opcoder.vhd signals into pipeline's stage 0.
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-- Incoming from opcoder.vhd signals into pipeline's stage 0.
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