| Line 25... |
Line 25... |
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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--! Paquete para el manejo de aritmŽtica con signo sobre el tipo std_logic_vector
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--! Paquete para el manejo de aritmŽtica con signo sobre el tipo std_logic_vector
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use ieee.std_logic_signed.all;
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use ieee.std_logic_signed.all;
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--! Paquete estandar de texto
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use std.textio.all;
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--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
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--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
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use work.arithpack.all;
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use work.arithpack.all;
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--! uf es la descripción del circuito que realiza la aritmética del Rt Engine.
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--! uf es la descripción del circuito que realiza la aritmética del Rt Engine.
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| Line 40... |
Line 43... |
--! La característica fundamental de uf, es que puede realizar 2 operaciones de producto punto al mimso tiempo ó una operación de producto cruz al mismo tiempo. La otra característica importante es que el pipe de producto punto es mas largo que el pipe de producto cruz: el producto punto tomará 3 clocks para realizarse, mientras que el procto punto tomara 4 clocks para realizarse.
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--! La característica fundamental de uf, es que puede realizar 2 operaciones de producto punto al mimso tiempo ó una operación de producto cruz al mismo tiempo. La otra característica importante es que el pipe de producto punto es mas largo que el pipe de producto cruz: el producto punto tomará 3 clocks para realizarse, mientras que el procto punto tomara 4 clocks para realizarse.
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entity uf is
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entity uf is
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generic (
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generic (
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use_std_logic_signed : string := "NO";
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use_std_logic_signed : string := "NO";
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testbench_generation : string := "NO";
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carry_logic : string := "CLA"
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carry_logic : string := "CLA"
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);
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);
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port (
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port (
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opcode : in std_logic; --! Entrada que dentro de la arquitectura funciona como selector de la operación que se lleva a cabo en la primera etapa de sumadores/restadores.
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opcode : in std_logic; --! Entrada que dentro de la arquitectura funciona como selector de la operación que se lleva a cabo en la primera etapa de sumadores/restadores.
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0); --! Entradas que van conectadas a los multiplicadores en la primera etapa de la descripción.
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m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0); --! Entradas que van conectadas a los multiplicadores en la primera etapa de la descripción.
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| Line 77... |
Line 81... |
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begin
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begin
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-- Multiplicator Instantiation (StAgE 0)
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-- Multiplicator Instantiation (StAgE 0)
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--! Multiplicador 0
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--! Multiplicador 0
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m0 : r_a18_b18_smul_c32_r
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m0 : lpm_mult
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generic map (
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_pipeline => 2,
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lpm_representation => "SIGNED",
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lpm_type => "LPM_MULT",
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lpm_widtha => 18,
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lpm_widthb => 18,
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lpm_widthp => 32
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)
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => stage0mf00,
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dataa => stage0mf00,
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datab => stage0mf01,
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datab => stage0mf01,
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result => stage0p0
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result => stage0p0
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);
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);
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--! Multiplicador 1
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--! Multiplicador 1
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m1 : r_a18_b18_smul_c32_r
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m1 : lpm_mult
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generic map (
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_pipeline => 2,
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lpm_representation => "SIGNED",
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lpm_type => "LPM_MULT",
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lpm_widtha => 18,
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lpm_widthb => 18,
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lpm_widthp => 32
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)
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => stage0mf10,
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dataa => stage0mf10,
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datab => stage0mf11,
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datab => stage0mf11,
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result => stage0p1
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result => stage0p1
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);
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);
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--! Multiplicador 2
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--! Multiplicador 2
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m2 : r_a18_b18_smul_c32_r
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m2 : lpm_mult
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generic map (
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_pipeline => 2,
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lpm_representation => "SIGNED",
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lpm_type => "LPM_MULT",
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lpm_widtha => 18,
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lpm_widthb => 18,
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lpm_widthp => 32
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)
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => stage0mf20,
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dataa => stage0mf20,
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datab => stage0mf21,
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datab => stage0mf21,
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result => stage0p2
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result => stage0p2
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);
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);
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--! Multiplicador 3
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--! Multiplicador 3
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m3 : r_a18_b18_smul_c32_r
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m3 : lpm_mult
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generic map (
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_pipeline => 2,
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lpm_representation => "SIGNED",
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lpm_type => "LPM_MULT",
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lpm_widtha => 18,
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lpm_widthb => 18,
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lpm_widthp => 32
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)
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => stage0mf30,
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dataa => stage0mf30,
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datab => stage0mf31,
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datab => stage0mf31,
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result => stage0p3
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result => stage0p3
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);
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);
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--! Multiplicador 4
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--! Multiplicador 4
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m4 : r_a18_b18_smul_c32_r
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m4 : lpm_mult
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generic map (
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_pipeline => 2,
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lpm_representation => "SIGNED",
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lpm_type => "LPM_MULT",
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lpm_widtha => 18,
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lpm_widthb => 18,
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lpm_widthp => 32
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)
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => stage0mf40,
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dataa => stage0mf40,
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datab => stage0mf41,
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datab => stage0mf41,
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result => stage0p4
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result => stage0p4
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);
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);
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--! Multiplicador 5
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--! Multiplicador 5
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m5 : r_a18_b18_smul_c32_r
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m5 : lpm_mult
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generic map (
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lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_pipeline => 2,
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lpm_representation => "SIGNED",
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lpm_type => "LPM_MULT",
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lpm_widtha => 18,
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lpm_widthb => 18,
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lpm_widthp => 32
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)
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port map (
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port map (
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aclr => rst,
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aclr => rst,
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clock => clk,
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clock => clk,
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dataa => stage0mf50,
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dataa => stage0mf50,
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datab => stage0mf51,
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datab => stage0mf51,
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| Line 275... |
Line 333... |
stageSRopcode <= stageMopcode;
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stageSRopcode <= stageMopcode;
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end if;
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end if;
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end process uf_seq;
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end process uf_seq;
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--! Codigo generado para realizar test bench
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tbgen:
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if testbench_generation="YES" generate
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tbproc0:
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process
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variable buff : line;
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file mbuff : text open write_mode is "TRACE_multiplier_content";
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begin
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write(buff,string'("UF multipliers test benching"));
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writeline(mbuff, buff);
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wait for 5 ns;
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wait until rst=not(rstMasterValue);
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wait until clk='1';
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wait for tclk2+tclk4; --! Garantizar la estabilidad de los datos que se van a observar en la salida.
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displayRom:
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loop
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write (buff,now,unit =>ns);
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write (buff,string'(" "));
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hexwrite_0 (buff,stage1p0(31 downto 0));
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write (buff,string'(" "));
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hexwrite_0 (buff,stage1p1(31 downto 0));
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write (buff,string'(" "));
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hexwrite_0 (buff,stage1p2(31 downto 0));
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write (buff,string'(" "));
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hexwrite_0 (buff,stage1p1(31 downto 0));
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write (buff,string'(" "));
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hexwrite_0 (buff,stage1p4(31 downto 0));
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write (buff,string'(" "));
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hexwrite_0 (buff,stage1p5(31 downto 0));
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writeline(mbuff,buff);
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wait for tclk;
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end loop displayRom;
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end process tbproc0;
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tbproc1:
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process
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variable buff : line;
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file fbuff : text open write_mode is "TRACE_decoded_factors_content";
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begin
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write(buff,string'("UF factors decoded test benching"));
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writeline(fbuff, buff);
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wait for 5 ns;
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wait until rst=not(rstMasterValue);
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wait until clk='1';
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wait for tclk2+tclk4; --! Garantizar la estabilidad de los datos que se van a observar en la salida.
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displayRom:
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loop
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write (buff,now,unit =>ns);
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write (buff,string'(" {"));
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hexwrite_0 (buff,m0f0(17 downto 0));
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hexwrite_0 (buff,m0f1(17 downto 0));
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write (buff,string'("} {"));
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hexwrite_0 (buff,m1f0(17 downto 0));
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hexwrite_0 (buff,m1f1(17 downto 0));
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write (buff,string'("} {"));
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hexwrite_0 (buff,m2f0(17 downto 0));
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hexwrite_0 (buff,m2f1(17 downto 0));
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write (buff,string'("} {"));
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hexwrite_0 (buff,m3f0(17 downto 0));
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hexwrite_0 (buff,m3f1(17 downto 0));
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write (buff,string'("} {"));
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hexwrite_0 (buff,m4f0(17 downto 0));
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hexwrite_0 (buff,m4f1(17 downto 0));
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write (buff,string'("} {"));
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hexwrite_0 (buff,m5f0(17 downto 0));
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hexwrite_0 (buff,m5f1(17 downto 0));
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write (buff,string'("}"));
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writeline(fbuff,buff);
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wait for tclk;
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end loop displayRom;
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end process tbproc1;
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tbproc2:
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process
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variable buff : line;
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file rbuff : text open write_mode is "TRACE_results_content";
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begin
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write(buff,string'("UF results test benching"));
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writeline(rbuff, buff);
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wait for 5 ns;
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wait until rst=not(rstMasterValue);
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wait until clk='1';
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wait for tclk2+tclk4; --! Garantizar la estabilidad de los datos que se van a observar en la salida.
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displayRom:
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loop
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write (buff,now,unit =>ns);
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write (buff,string'(" {"));
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hexwrite_0 (buff,stage1a0(31 downto 0));
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write (buff,string'(" "));
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hexwrite_0 (buff,stage1a1(31 downto 0));
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write (buff,string'(" "));
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hexwrite_0 (buff,stage1a2(31 downto 0));
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write (buff,string'("} {dp0: "));
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hexwrite_0 (buff,stage2a3(31 downto 0));
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write (buff,string'(",dp1: "));
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hexwrite_0 (buff,stage2a4(31 downto 0));
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write (buff,string'("}"));
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writeline(rbuff,buff);
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wait for tclk;
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end loop displayRom;
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end process tbproc2;
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end generate tbgen;
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end uf_arch;
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end uf_arch;
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No newline at end of file
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No newline at end of file
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