| Line 49... |
Line 49... |
carry_logic : string := "CLA"
|
carry_logic : string := "CLA"
|
);
|
);
|
port (
|
port (
|
opcode : in std_logic; --! Entrada que dentro de la arquitectura funciona como selector de la operación que se lleva a cabo en la primera etapa de sumadores/restadores.
|
opcode : in std_logic; --! Entrada que dentro de la arquitectura funciona como selector de la operación que se lleva a cabo en la primera etapa de sumadores/restadores.
|
m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0); --! Entradas que van conectadas a los multiplicadores en la primera etapa de la descripción.
|
m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0); --! Entradas que van conectadas a los multiplicadores en la primera etapa de la descripción.
|
cpx,cpy,cpz,dp0,dp1 : out std_logic_vector(31 downto 0); --! Salidas donde se registran los resultados de las operaciones aritméticas: cpx,cpy,cpz ser´n los componentes del vector que da por resultado el producto cruz entre los vectores AxB ó CxD.
|
cpx,cpy,cpz,dp0,dp1,kvx0,kvy0,kvz0,kvx1,kvy1,kvz1 : out std_logic_vector(31 downto 0); --! Salidas donde se registran los resultados de las operaciones aritméticas: cpx,cpy,cpz ser´n los componentes del vector que da por resultado el producto cruz entre los vectores AxB ó CxD. kvx0, kvy0, kvz0, kvx1, kvy1, kvz1 es el resultado de los multiplicadores
|
clk,rst : in std_logic --! Las entradas de control usuales.
|
clk,rst : in std_logic --! Las entradas de control usuales.
|
);
|
);
|
end uf;
|
end uf;
|
|
|
architecture uf_arch of uf is
|
architecture uf_arch of uf is
|
| Line 98... |
Line 98... |
clock => clk,
|
clock => clk,
|
dataa => stage0mf00,
|
dataa => stage0mf00,
|
datab => stage0mf01,
|
datab => stage0mf01,
|
result => stage0p0
|
result => stage0p0
|
);
|
);
|
|
kvx0 <= stage0p0;
|
--! Multiplicador 1
|
--! Multiplicador 1
|
m1 : lpm_mult
|
m1 : lpm_mult
|
generic map (
|
generic map (
|
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
|
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
|
lpm_pipeline => 2,
|
lpm_pipeline => 2,
|
| Line 117... |
Line 117... |
clock => clk,
|
clock => clk,
|
dataa => stage0mf10,
|
dataa => stage0mf10,
|
datab => stage0mf11,
|
datab => stage0mf11,
|
result => stage0p1
|
result => stage0p1
|
);
|
);
|
|
kvy0 <= stage0p1;
|
|
|
--! Multiplicador 2
|
--! Multiplicador 2
|
m2 : lpm_mult
|
m2 : lpm_mult
|
generic map (
|
generic map (
|
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
|
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
|
| Line 136... |
Line 137... |
clock => clk,
|
clock => clk,
|
dataa => stage0mf20,
|
dataa => stage0mf20,
|
datab => stage0mf21,
|
datab => stage0mf21,
|
result => stage0p2
|
result => stage0p2
|
);
|
);
|
|
kvz0 <= stage0p2;
|
|
|
--! Multiplicador 3
|
--! Multiplicador 3
|
m3 : lpm_mult
|
m3 : lpm_mult
|
generic map (
|
generic map (
|
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
|
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
|
| Line 155... |
Line 157... |
clock => clk,
|
clock => clk,
|
dataa => stage0mf30,
|
dataa => stage0mf30,
|
datab => stage0mf31,
|
datab => stage0mf31,
|
result => stage0p3
|
result => stage0p3
|
);
|
);
|
|
kvx1 <= stage0p3;
|
--! Multiplicador 4
|
--! Multiplicador 4
|
m4 : lpm_mult
|
m4 : lpm_mult
|
generic map (
|
generic map (
|
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
|
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
|
lpm_pipeline => 2,
|
lpm_pipeline => 2,
|
| Line 174... |
Line 176... |
clock => clk,
|
clock => clk,
|
dataa => stage0mf40,
|
dataa => stage0mf40,
|
datab => stage0mf41,
|
datab => stage0mf41,
|
result => stage0p4
|
result => stage0p4
|
);
|
);
|
|
kvy1 <= stage0p4;
|
|
|
--! Multiplicador 5
|
--! Multiplicador 5
|
m5 : lpm_mult
|
m5 : lpm_mult
|
generic map (
|
generic map (
|
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
|
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
|
| Line 193... |
Line 196... |
clock => clk,
|
clock => clk,
|
dataa => stage0mf50,
|
dataa => stage0mf50,
|
datab => stage0mf51,
|
datab => stage0mf51,
|
result => stage0p5
|
result => stage0p5
|
);
|
);
|
|
kvz1 <= stage0p5;
|
|
|
|
|
useIeee:
|
useIeee:
|
if use_std_logic_signed="YES" generate
|
if use_std_logic_signed="YES" generate
|
-- Adder Instantiation (sTaGe 1)
|
-- Adder Instantiation (sTaGe 1)
|
| Line 216... |
Line 219... |
stage1a1 <= stage1p2-stage1p3; -- This is always going to be a substraction
|
stage1a1 <= stage1p2-stage1p3; -- This is always going to be a substraction
|
|
|
-- Adder Instantiation (Stage 2)
|
-- Adder Instantiation (Stage 2)
|
stage2a3 <= stage2a0+stage2p2;
|
stage2a3 <= stage2a0+stage2p2;
|
stage2a4 <= stage2p3+stage2a2;
|
stage2a4 <= stage2p3+stage2a2;
|
|
|
end generate useIeee;
|
end generate useIeee;
|
dontUseIeee:
|
dontUseIeee:
|
if use_std_logic_signed="NO" generate
|
if use_std_logic_signed="NO" generate
|
--! Adder 0, 16 bit carry lookahead low adder.
|
--! Adder 0, 16 bit carry lookahead low adder.
|
a0low : adder
|
a0low : adder
|
