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The core is *WISHBONE* B.3 master compatible.
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The core is *WISHBONE* B.3 master compatible.
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Supported cycles: master read/write, master read/modify/write
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Supported cycles: master read/write, master read/modify/write
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Address and data bus are both 32-bits wide.
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Address and data bus are both 32-bits wide.
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## Size / Performance
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## Size / Performance
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approx. 13,000 LUTs (21,000 LC's), approx <80 MHz max (in -1 part).
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approx. 13,000 LUTs (21,000 LC's) without FP, approx <80 MHz max (in -1 part).
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No idea how the cycle times compare to a stock 68000, but suspect it may be a little faster due to minimum bus cycle time of two clocks and a 32-bit data bus.
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No idea how the cycle times compare to a stock 68000, but suspect it may be a little faster due to minimum bus cycle time of two clocks and a 32-bit data bus.
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## Software
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## Software
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The core may use 68000 software. There is a modified 68k vasm assembler. Additional control registers were added for movec.
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The core may use 68000 software. There is a modified 68k vasm assembler. Additional control registers were added for movec.
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There are some software examples in the examples folder.
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There are some software examples in the examples folder.
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## Instruction Set
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The core includes BCD to binary and binary to BCD conversion functions in addition to the standard 68k instructions.
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### Floating-Point
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The core supports 96-bit triple precision decimal floating-point. The core repurposes the packed BCD floating-point instructions to implement triple precision densely-packed-decimal floating point. This may be
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disabled by commenting out the 'SUPPORT_DECFLT' definition to reduce the core
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size.
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The following floating-point instructions are at least partially supported:
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FADD, FSUB, FMUL, FDIV, FNEG, FSCALE, FCMP, FTST, FBcc, FMOVE
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## License
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## License
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BSD-3
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BSD-3
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## Other 68k Cores
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## Other 68k Cores
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http://www.opencores.org/project,ao68000
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http://www.opencores.org/project,ao68000
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