URL https://opencores.org/ocsvn/rf68000/rf68000/trunk

Subversion Repositories rf68000

[/] [rf68000/] [trunk/] [rtl/] [cpu/] [io_bitmap.sv] - Diff between revs 2 and 3

Rev 2	Rev 3
Line 146...	Line 146...
`// on the data output of port A.`	`// on the data output of port A.`

`.sbiterrb(), // 1-bit output: Status signal to indicate single bit error occurrence`	`.sbiterrb(), // 1-bit output: Status signal to indicate single bit error occurrence`
`// on the data output of port B.`	`// on the data output of port B.`

`.addra({asid_i[5:0],adr_i[ 8: 2]}), // ADDR_WIDTH_A-bit input: Address for port A write and read operations.`	`.addra(adr_i[14: 2]), // ADDR_WIDTH_A-bit input: Address for port A write and read operations.`
`.addrb({asid_i[5:0],adr_i[19:13]}), // ADDR_WIDTH_B-bit input: Address for port B write and read operations.`	`.addrb({asid_i[5:0],adr_i[19:13]}), // ADDR_WIDTH_B-bit input: Address for port B write and read operations.`
`.clka(clk_i), // 1-bit input: Clock signal for port A. Also clocks port B when`	`.clka(clk_i), // 1-bit input: Clock signal for port A. Also clocks port B when`
`// parameter CLOCKING_MODE is "common_clock".`	`// parameter CLOCKING_MODE is "common_clock".`

`.clkb(clk_i), // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is`	`.clkb(clk_i), // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is`
Line 218...	Line 218...
`if (ena)`	`if (ena)`
`dat_o <= douta;`	`dat_o <= douta;`
`else`	`else`
`dat_o <= 32'd0;`	`dat_o <= 32'd0;`

`always_comb`	`always_ff @(posedge clk_i)`
`gate_o <= doutb[adr_i[12:8]];`	`gate_o <= doutb[adr_i[12:8]] & enb;`

`endmodule`	`endmodule`