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https://opencores.org/ocsvn/rf68000/rf68000/trunk
[/] [rf68000/] [trunk/] [rtl/] [cpu/] [io_bitmap.sv] - Diff between revs 2 and 3
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// on the data output of port A.
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// on the data output of port A.
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.sbiterrb(), // 1-bit output: Status signal to indicate single bit error occurrence
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.sbiterrb(), // 1-bit output: Status signal to indicate single bit error occurrence
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// on the data output of port B.
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// on the data output of port B.
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.addra({asid_i[5:0],adr_i[ 8: 2]}), // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
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.addra(adr_i[14: 2]), // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
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.addrb({asid_i[5:0],adr_i[19:13]}), // ADDR_WIDTH_B-bit input: Address for port B write and read operations.
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.addrb({asid_i[5:0],adr_i[19:13]}), // ADDR_WIDTH_B-bit input: Address for port B write and read operations.
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.clka(clk_i), // 1-bit input: Clock signal for port A. Also clocks port B when
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.clka(clk_i), // 1-bit input: Clock signal for port A. Also clocks port B when
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// parameter CLOCKING_MODE is "common_clock".
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// parameter CLOCKING_MODE is "common_clock".
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.clkb(clk_i), // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
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.clkb(clk_i), // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
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if (ena)
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if (ena)
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dat_o <= douta;
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dat_o <= douta;
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else
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else
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dat_o <= 32'd0;
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dat_o <= 32'd0;
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always_comb
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always_ff @(posedge clk_i)
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gate_o <= doutb[adr_i[12:8]];
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gate_o <= doutb[adr_i[12:8]] & enb;
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endmodule
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endmodule
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