| Line 46... |
Line 46... |
`define SUPPORT_DIV 1'b1
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`define SUPPORT_DIV 1'b1
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`define SUPPORT_BCD 1'b1
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`define SUPPORT_BCD 1'b1
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//`define SUPPORT_010 1'b1
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//`define SUPPORT_010 1'b1
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`define SUPPORT_BITPAIRS 1'b1
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`define SUPPORT_BITPAIRS 1'b1
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|
|
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//`define HAS_MMU 1'b1
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|
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//`define SUPPORT_TASK 1'b1
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//`define SUPPORT_TASK 1'b1
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|
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//`define SUPPORT_B24 1'b1 // To support 23-bit branch displacements
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//`define SUPPORT_B24 1'b1 // To support 23-bit branch displacements
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|
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`define TRUE 1'b1
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`define TRUE 1'b1
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| Line 91... |
Line 93... |
`define LDW 16'b0011_xxx0xx_xxxxxx
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`define LDW 16'b0011_xxx0xx_xxxxxx
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`define STB 16'b0001_xxx1xx_xxxxxx
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`define STB 16'b0001_xxx1xx_xxxxxx
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`define STH 16'b0010_xxx1xx_xxxxxx
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`define STH 16'b0010_xxx1xx_xxxxxx
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`define STW 16'b0011_xxx1xx_xxxxxx
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`define STW 16'b0011_xxx1xx_xxxxxx
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|
|
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// DBcc also for Scc
|
`define DBRA 8'h50
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`define DBRA 8'h50
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`define DBSR 8'h51
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`define DBSR 8'h51
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`define DBHI 8'h52
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`define DBHI 8'h52
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`define DBLS 8'h53
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`define DBLS 8'h53
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`define DBHS 8'h54
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`define DBHS 8'h54
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| Line 470... |
Line 473... |
reg [31:0] a3 = 'd0;
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reg [31:0] a3 = 'd0;
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reg [31:0] a4 = 'd0;
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reg [31:0] a4 = 'd0;
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reg [31:0] a5 = 'd0;
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reg [31:0] a5 = 'd0;
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reg [31:0] a6 = 'd0;
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reg [31:0] a6 = 'd0;
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reg [31:0] sp = 'd0;
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reg [31:0] sp = 'd0;
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reg [127:0] fp0 = 'd0;
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reg [127:0] fp1 = 'd0;
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reg [127:0] fp2 = 'd0;
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reg [127:0] fp3 = 'd0;
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reg [127:0] fp4 = 'd0;
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|
reg [127:0] fp5 = 'd0;
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reg [127:0] fp6 = 'd0;
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reg [127:0] fp7 = 'd0;
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reg [31:0] d0i;
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reg [31:0] d0i;
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reg [31:0] d1i;
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reg [31:0] d1i;
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reg [31:0] d2i;
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reg [31:0] d2i;
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reg [31:0] d3i;
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reg [31:0] d3i;
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reg [31:0] d4i;
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reg [31:0] d4i;
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| Line 637... |
Line 648... |
//wire [31:0] rfob = {mmm[0],rrr}==4'b1111 ? sp : regfile[{mmm[0],rrr}];
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//wire [31:0] rfob = {mmm[0],rrr}==4'b1111 ? sp : regfile[{mmm[0],rrr}];
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//wire [31:0] rfoDnn = regfile[{1'b0,rrr}];
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//wire [31:0] rfoDnn = regfile[{1'b0,rrr}];
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//wire [31:0] rfoRnn = rrrr==4'b1111 ? sp : regfile[rrrr];
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//wire [31:0] rfoRnn = rrrr==4'b1111 ? sp : regfile[rrrr];
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wire clk_g;
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wire clk_g;
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reg rfwrL,rfwrB,rfwrW;
|
reg rfwrL,rfwrB,rfwrW;
|
|
reg rfwrFp;
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reg takb;
|
reg takb;
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reg [8:0] resB;
|
reg [8:0] resB;
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reg [16:0] resW;
|
reg [16:0] resW;
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reg [32:0] resL;
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reg [32:0] resL;
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(* USE_DSP = "no" *)
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(* USE_DSP = "no" *)
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| Line 678... |
Line 690... |
reg [31:0] apc;
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reg [31:0] apc;
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reg [7:0] cpl;
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reg [7:0] cpl;
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reg [31:0] tr;
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reg [31:0] tr;
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reg [31:0] tcba;
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reg [31:0] tcba;
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reg [31:0] mmus, ios, iops;
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reg [31:0] mmus, ios, iops;
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assign mmus_o = adr_o[31:2] >= mmus[31:2] && adr_o[31:2] < mmus[31:2]+10'd512;
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assign mmus_o = adr_o[31:20] == mmus[31:20];
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assign iops_o = adr_o[31:2] >= iops[31:2] && adr_o[31:2] < iops[31:2]+8'd128;
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assign iops_o = adr_o[31:16] == iops[31:16];
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assign ios_o = adr_o[31:2] >= ios [31:2] && adr_o[31:2] < ios [31:2]+24'h100000;
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assign ios_o = adr_o[31:20] == ios [31:20];
|
|
|
wire [16:0] lfsr_o;
|
wire [16:0] lfsr_o;
|
lfsr17 ulfsr1
|
lfsr17 ulfsr1
|
(
|
(
|
.rst(rst_i),
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.rst(rst_i),
|
| Line 1553... |
Line 1565... |
fc_o <= {sf,2'b10};
|
fc_o <= {sf,2'b10};
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 4'b1111;
|
sel_o <= 4'b1111;
|
adr_o <= pc;
|
adr_o <= pc;
|
|
goto (IFETCH);
|
end
|
end
|
end
|
end
|
else if (ack_i) begin
|
else if (ack_i) begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
| Line 1573... |
Line 1586... |
fc_o <= {sf,2'b10};
|
fc_o <= {sf,2'b10};
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 4'b1111;
|
sel_o <= 4'b1111;
|
adr_o <= pc;
|
adr_o <= pc;
|
|
goto (IFETCH2);
|
end
|
end
|
else if (ack_i) begin
|
else if (ack_i) begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 2'b00;
|
sel_o <= 2'b00;
|
| Line 1922... |
Line 1936... |
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// ADDQ / SUBQ / DBRA / Scc
|
// ADDQ / SUBQ / DBRA / Scc
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
5'h5:
|
5'h5:
|
begin
|
begin
|
casez(ir[7:4])
|
casez(ir[7:3])
|
// When optimizing DBRA for performance, the memory access cycle to fetch
|
// When optimizing DBRA for performance, the memory access cycle to fetch
|
// the displacement constant is not done, instead the PC is incremented by
|
// the displacement constant is not done, instead the PC is incremented by
|
// two if not doing the DBRA. This is an extra PC increment that increases
|
// two if not doing the DBRA. This is an extra PC increment that increases
|
// the code size. It is slower, but more hardware efficient to just always
|
// the code size. It is slower, but more hardware efficient to just always
|
// fetch the displacement.
|
// fetch the displacement.
|
4'b1100: // DBRA
|
5'b11001: // DBRA
|
`ifdef OPT_PERF
|
`ifdef OPT_PERF
|
if (~takb) begin
|
if (~takb) begin
|
call(FETCH_IMM16,DBRA);
|
call(FETCH_IMM16,DBRA);
|
end
|
end
|
else begin
|
else begin
|
| Line 1940... |
Line 1954... |
ret();
|
ret();
|
end
|
end
|
`else
|
`else
|
call(FETCH_IMM16,DBRA);
|
call(FETCH_IMM16,DBRA);
|
`endif
|
`endif
|
4'b11??: // Scc
|
5'b11???: // Scc
|
begin
|
begin
|
resL <= {32{takb}};
|
resL <= {32{takb}};
|
resW <= {16{takb}};
|
resW <= {16{takb}};
|
resB <= {8{takb}};
|
resB <= {8{takb}};
|
d <= {32{takb}};
|
d <= {32{takb}};
|
| Line 5389... |
Line 5403... |
end
|
end
|
MOVERn2Rc2:
|
MOVERn2Rc2:
|
case(imm[11:0])
|
case(imm[11:0])
|
12'h000: begin sfc <= rfoRnn; ret(); end
|
12'h000: begin sfc <= rfoRnn; ret(); end
|
12'h001: begin dfc <= rfoRnn; ret(); end
|
12'h001: begin dfc <= rfoRnn; ret(); end
|
12'h003: begin asid <= rfoDnn[7:0]; ret(); end
|
12'h003: begin asid <= rfoRnn[7:0]; ret(); end
|
12'h010: begin apc <= rfoDnn; ret(); end
|
12'h010: begin apc <= rfoRnn; ret(); end
|
12'h011: begin cpl <= rfoDnn[7:0]; ret(); end
|
12'h011: begin cpl <= rfoRnn[7:0]; ret(); end
|
12'h012: begin tr <= rfoDnn; ret(); end
|
12'h012: begin tr <= rfoRnn; ret(); end
|
12'h013: begin tcba <= rfoDnn; ret(); end
|
12'h013: begin tcba <= rfoRnn; ret(); end
|
12'h014: begin mmus <= rfoDnn; ret(); end
|
12'h014: begin mmus <= rfoRnn; ret(); end
|
12'h015: begin ios <= rfoDnn; ret(); end
|
12'h015: begin ios <= rfoRnn; ret(); end
|
12'h016: begin iops <= rfoDnn; ret(); end
|
12'h016: begin iops <= rfoRnn; ret(); end
|
12'h800: begin usp <= rfoRnn; ret(); end
|
12'h800: begin usp <= rfoRnn; ret(); end
|
12'h801: begin vbr <= rfoRnn; ret(); end
|
12'h801: begin vbr <= rfoRnn; ret(); end
|
/*
|
/*
|
12'hFE1:
|
12'hFE1:
|
begin
|
begin
|
