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[/] [rf68000/] [trunk/] [rtl/] [cpu/] [rf68000.sv] - Diff between revs 3 and 4

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Line 46... Line 46...
`define SUPPORT_DIV     1'b1
`define SUPPORT_DIV     1'b1
`define SUPPORT_BCD     1'b1
`define SUPPORT_BCD     1'b1
//`define SUPPORT_010   1'b1
//`define SUPPORT_010   1'b1
`define SUPPORT_BITPAIRS 1'b1
`define SUPPORT_BITPAIRS 1'b1
 
 
 
`define SUPPORT_DECFLT 1'b1
 
 
//`define HAS_MMU 1'b1
//`define HAS_MMU 1'b1
 
 
//`define SUPPORT_TASK  1'b1
//`define SUPPORT_TASK  1'b1
 
 
//`define SUPPORT_B24   1'b1            // To support 23-bit branch displacements
//`define SUPPORT_B24   1'b1            // To support 23-bit branch displacements
Line 329... Line 331...
        BCD4,
        BCD4,
        OR,
        OR,
 
 
        INT,
        INT,
        INT2,
        INT2,
        INT3,
 
 
 
        // 150
        // 150
 
        INT3,
        INT4,
        INT4,
 
 
        MOVEM_Xn2D,
        MOVEM_Xn2D,
        MOVEM_Xn2D2,
        MOVEM_Xn2D2,
        MOVEM_Xn2D3,
        MOVEM_Xn2D3,
Line 343... Line 345...
        MOVEM_s2Xn,
        MOVEM_s2Xn,
        MOVEM_s2Xn2,
        MOVEM_s2Xn2,
        MOVEM_s2Xn3,
        MOVEM_s2Xn3,
 
 
        TASK1,
        TASK1,
        THREAD2,
 
 
 
        // 160
        // 160
 
        THREAD2,
        TASK3,
        TASK3,
        TASK4,
        TASK4,
 
 
        LDT1,
        LDT1,
        LDT2,
        LDT2,
Line 357... Line 359...
        SDT1,
        SDT1,
        SDT2,
        SDT2,
 
 
        SUB,
        SUB,
        SUB1,
        SUB1,
 
 
 
        // 170
        MOVEP,
        MOVEP,
        MOVEP1,
        MOVEP1,
        MOVEP2,
        MOVEP2,
        MOVEP3,
        MOVEP3,
        CHK,
        CHK,
Line 369... Line 373...
        MOVERn2Rc,
        MOVERn2Rc,
        MOVERn2Rc2,
        MOVERn2Rc2,
 
 
        MOVES,
        MOVES,
        MOVES2,
        MOVES2,
 
 
 
        // 180
        MOVES3,
        MOVES3,
 
 
        ADDX,
        ADDX,
        ADDX2,
        ADDX2,
        ADDX3,
        ADDX3,
Line 382... Line 388...
 
 
        MULU1,
        MULU1,
        MULU2,
        MULU2,
        MULU3,
        MULU3,
 
 
 
        //190
        MULS1,
        MULS1,
        MULS2,
        MULS2,
        MULS3,
        MULS3,
 
 
        BIN2BCD1,
        BIN2BCD1,
Line 393... Line 400...
        BCD2BIN1,
        BCD2BIN1,
        BCD2BIN2,
        BCD2BIN2,
        BCD2BIN3,
        BCD2BIN3,
 
 
        IFETCH2,
        IFETCH2,
 
        FADD,
 
 
 
        // 200
 
        FCMP,
 
        FMUL1,
 
        FMUL2,
 
        FDIV1,
 
        FDIV2,
 
        FNEG,
 
        FMOVE,
 
        I2DF1,
 
        I2DF2,
 
        DF2I1,
 
        DF2I2,
 
        FTST,
 
        FBCC,
 
        FSCALE,
 
        FCOPYEXP,
 
 
 
        FETCH_HEXI1,
 
        FETCH_HEXI2,
 
        FETCH_HEXI3,
 
        FETCH_HEXI4,
 
        STORE_HEXI1,
 
        STORE_HEXI2,
 
        STORE_HEXI3,
 
        STORE_HEXI4,
 
 
        FSDATA2
        FSDATA2
} state_t;
} state_t;
 
 
typedef enum logic [4:0] {
typedef enum logic [4:0] {
Line 444... Line 478...
reg [31:0] adr_o;
reg [31:0] adr_o;
input [31:0] dat_i;
input [31:0] dat_i;
output [31:0] dat_o;
output [31:0] dat_o;
reg [31:0] dat_o;
reg [31:0] dat_o;
 
 
 
wire DECFLT = coreno_i==32'd2;
 
 
reg em;                                                 // emulation mode
reg em;                                                 // emulation mode
reg [15:0] ir;
reg [15:0] ir;
reg [15:0] ir2;                 // second word for ir
reg [15:0] ir2;                 // second word for ir
reg ext_ir;
reg ext_ir;
reg [31:0] icnt;
reg [31:0] icnt;
Line 473... Line 509...
reg [31:0] a3 = 'd0;
reg [31:0] a3 = 'd0;
reg [31:0] a4 = 'd0;
reg [31:0] a4 = 'd0;
reg [31:0] a5 = 'd0;
reg [31:0] a5 = 'd0;
reg [31:0] a6 = 'd0;
reg [31:0] a6 = 'd0;
reg [31:0] sp = 'd0;
reg [31:0] sp = 'd0;
reg [127:0] fp0 = 'd0;
reg [95:0] fp0 = 'd0;
reg [127:0] fp1 = 'd0;
reg [95:0] fp1 = 'd0;
reg [127:0] fp2 = 'd0;
reg [95:0] fp2 = 'd0;
reg [127:0] fp3 = 'd0;
reg [95:0] fp3 = 'd0;
reg [127:0] fp4 = 'd0;
reg [95:0] fp4 = 'd0;
reg [127:0] fp5 = 'd0;
reg [95:0] fp5 = 'd0;
reg [127:0] fp6 = 'd0;
reg [95:0] fp6 = 'd0;
reg [127:0] fp7 = 'd0;
reg [95:0] fp7 = 'd0;
reg [31:0] d0i;
reg [31:0] d0i;
reg [31:0] d1i;
reg [31:0] d1i;
reg [31:0] d2i;
reg [31:0] d2i;
reg [31:0] d3i;
reg [31:0] d3i;
reg [31:0] d4i;
reg [31:0] d4i;
Line 524... Line 560...
reg [2:0] ccr57;
reg [2:0] ccr57;
reg [1:0] sr1112;
reg [1:0] sr1112;
reg sr14;
reg sr14;
wire [15:0] sr = {tf,sr14,sf,sr1112,im,ccr57,xf,nf,zf,vf,cf};
wire [15:0] sr = {tf,sr14,sf,sr1112,im,ccr57,xf,nf,zf,vf,cf};
wire [31:0] srx = {sr};
wire [31:0] srx = {sr};
 
reg fnf,fzf,fvf,fnanf;
 
wire finff = fvf;
 
reg [7:0] quotient_bits;
 
reg [7:0] fpexc,fpaexc;
 
wire [31:0] fpsr = {4'h0,fnf,fzf,fvf,fnanf,quotient_bits,fpexc,fpaexc};
reg [31:0] isr;
reg [31:0] isr;
reg [3:0] ifmt;
reg [3:0] ifmt;
 
reg [7:0] fpcnt;
reg [31:0] pc;
reg [31:0] pc;
reg [31:0] opc;                 // pc for branch references
reg [31:0] opc;                 // pc for branch references
reg [31:0] ssp,usp;
reg [31:0] ssp,usp;
reg [31:0] disp;
reg [31:0] disp;
reg [31:0] s,d,dd,imm,immx;
reg [31:0] s,d,dd,imm,immx;
Line 549... Line 591...
wire [2:0] MMM = ir[8:6];
wire [2:0] MMM = ir[8:6];
wire [2:0] RRR = ir[11:9];
wire [2:0] RRR = ir[11:9];
wire [2:0] QQQ = ir[11:9];
wire [2:0] QQQ = ir[11:9];
wire [2:0] DDD = ir[11:9];
wire [2:0] DDD = ir[11:9];
wire [2:0] AAA = ir[11:9];
wire [2:0] AAA = ir[11:9];
 
reg [2:0] FLTSRC;
 
reg [2:0] FLTDST;
reg MMMRRR;
reg MMMRRR;
wire Anabit;
wire Anabit;
wire [31:0] sp_dec = sp - 32'd2;
wire [31:0] sp_dec = sp - 32'd2;
reg [31:0] rfoAn;
reg [31:0] rfoAn;
always_comb
always_comb
Line 641... Line 685...
4'd12:  rfoRnn <= a4;
4'd12:  rfoRnn <= a4;
4'd13:  rfoRnn <= a5;
4'd13:  rfoRnn <= a5;
4'd14:  rfoRnn <= a6;
4'd14:  rfoRnn <= a6;
4'd15:  rfoRnn <= sp;
4'd15:  rfoRnn <= sp;
endcase
endcase
 
reg [95:0] rfoFpdst, rfoFpsrc;
 
`ifdef SUPPORT_DECFLT
 
always_comb
 
case(FLTDST)
 
3'd0:   rfoFpdst <= fp0;
 
3'd1:   rfoFpdst <= fp1;
 
3'd2:   rfoFpdst <= fp2;
 
3'd3:   rfoFpdst <= fp3;
 
3'd4:   rfoFpdst <= fp4;
 
3'd5:   rfoFpdst <= fp5;
 
3'd6:   rfoFpdst <= fp6;
 
3'd7:   rfoFpdst <= fp7;
 
endcase
 
always_comb
 
case(FLTSRC)
 
3'd0:   rfoFpsrc <= fp0;
 
3'd1:   rfoFpsrc <= fp1;
 
3'd2:   rfoFpsrc <= fp2;
 
3'd3:   rfoFpsrc <= fp3;
 
3'd4:   rfoFpsrc <= fp4;
 
3'd5:   rfoFpsrc <= fp5;
 
3'd6:   rfoFpsrc <= fp6;
 
3'd7:   rfoFpsrc <= fp7;
 
endcase
 
`endif
//wire [31:0] rfoDn = regfile[{1'b0,DDD}];
//wire [31:0] rfoDn = regfile[{1'b0,DDD}];
//wire [31:0] rfoAna = AAA==3'b111 ? sp : regfile[{1'b1,AAA}];
//wire [31:0] rfoAna = AAA==3'b111 ? sp : regfile[{1'b1,AAA}];
//wire [31:0] rfob = {mmm[0],rrr}==4'b1111 ? sp : regfile[{mmm[0],rrr}];
//wire [31:0] rfob = {mmm[0],rrr}==4'b1111 ? sp : regfile[{mmm[0],rrr}];
//wire [31:0] rfoDnn = regfile[{1'b0,rrr}];
//wire [31:0] rfoDnn = regfile[{1'b0,rrr}];
//wire [31:0] rfoRnn = rrrr==4'b1111 ? sp : regfile[rrrr];
//wire [31:0] rfoRnn = rrrr==4'b1111 ? sp : regfile[rrrr];
wire clk_g;
wire clk_g;
reg rfwrL,rfwrB,rfwrW;
reg rfwrL,rfwrB,rfwrW;
reg rfwrFp;
reg rfwrF;
reg takb;
reg takb, ftakb;
reg [8:0] resB;
reg [8:0] resB;
reg [16:0] resW;
reg [16:0] resW;
reg [32:0] resL;
reg [32:0] resL;
 
reg [95:0] resF;
 
reg [95:0] fps, fpd;
(* USE_DSP = "no" *)
(* USE_DSP = "no" *)
reg [32:0] resL1,resL2;
reg [32:0] resL1,resL2;
reg [32:0] resMS1,resMS2,resMU1,resMU2;
reg [32:0] resMS1,resMS2,resMU1,resMU2;
reg [31:0] st_data;
reg [31:0] st_data;
wire [11:0] bcdaddo,bcdsubo,bcdnego;
wire [11:0] bcdaddo,bcdsubo,bcdnego;
Line 674... Line 745...
reg [4:0] rst_cnt;
reg [4:0] rst_cnt;
reg [2:0] shift_op;
reg [2:0] shift_op;
reg rtr;
reg rtr;
reg bsr;
reg bsr;
reg lea;
reg lea;
 
reg fsub;
reg bcdsub, bcdneg;
reg bcdsub, bcdneg;
reg [31:0] dati_buf;    // input data from bus error
reg [31:0] dati_buf;    // input data from bus error
reg [31:0] dato_buf;
reg [31:0] dato_buf;
 
 
// CSR's
// CSR's
Line 859... Line 931...
        .ovf(dvovf),
        .ovf(dvovf),
        .done(dvdone),
        .done(dvdone),
        .idle()
        .idle()
);
);
 
 
 
wire [95:0] dfaddsubo, dfmulo, dfdivo, i2dfo, df2io;
 
wire [95:0] dfscaleo;
 
wire dfmulinf;
 
wire dfmuldone, dfmulover, dfmulunder;
 
wire dfdivdone, dfdivover, dfdivunder;
 
wire [11:0] dfcmpo;
 
wire i2dfdone, df2idone;
 
wire df2iover;
 
//DFP96U fpsu, fpdu;
 
//DFP96 fpdp;
 
 
 
`ifdef SUPPORT_DECFLT
 
 
 
/*
 
assign fpdu.infinity = fpsu.infinity;
 
assign fpdu.nan = fpsu.nan;
 
assign fpdu.snan = fpsu.snan;
 
assign fpdu.qnan = fpsu.qnan;
 
assign fpdu.sign = fpsu.sign;
 
assign fpdu.exp = fpsu.exp;
 
assign fpdu.sig = {4'h1,24{4'h0}};
 
 
 
DFPPack upack1
 
(
 
        .i(fpdu),
 
        .o(fpdp)
 
);
 
 
 
DFPUnpack uunpack1
 
(
 
        .i(fps),
 
        .o(fpsu)
 
);
 
*/
 
 
 
DFPAddsub96nr ufaddsub1
 
(
 
        .clk(clk_g),
 
        .ce(1'b1),
 
        .rm(3'b0),
 
        .op(fsub),
 
        .a(fpd),
 
        .b(fps),
 
        .o(dfaddsubo)
 
);
 
 
 
DFPMultiply96nr udfmul1
 
(
 
        .clk(clk_g),
 
        .ce(1'b1),
 
        .ld(state==FMUL1),
 
        .a(fpd),
 
        .b(fps),
 
        .o(dfmulo),
 
        .rm(3'b000),
 
        .sign_exe(),
 
        .inf(dfmulinf),
 
        .overflow(dfmulover),
 
        .underflow(dfmulunder),
 
        .done(dfmuldone)
 
);
 
 
 
DFPDivide96nr udfdiv1
 
(
 
        .rst(rst_i),
 
        .clk(clk_g),
 
        .ce(1'b1),
 
        .ld(state==FDIV1),
 
        .op(1'b0),
 
        .a(fpd),
 
        .b(fps),
 
        .o(dfdivo),
 
        .rm(3'b000),
 
        .done(dfdivdone),
 
        .sign_exe(),
 
        .inf(),
 
        .overflow(dfdivover),
 
        .underflow(dfdivunder)
 
);
 
 
 
DFPCompare96 udfcmp1
 
(
 
        .a(fpd),
 
        .b(fps),
 
        .o(dfcmpo)
 
);
 
 
 
i2df96 ui2df1
 
(
 
        .rst(rst_i),
 
        .clk(clk_g),
 
        .ce(1'b1),
 
        .ld(state==I2DF1),
 
        .op(1'b0),      // 0=unsigned, 1= signed
 
        .rm(3'b000),
 
        .i(fps),
 
        .o(i2dfo),
 
        .done(i2dfdone)
 
);
 
 
 
df96Toi udf2i1 (
 
        .rst(rst_i),
 
        .clk(clk_g),
 
        .ce(1'b1),
 
        .ld(state==DF2I1),
 
        .op(1'b0),
 
        .i(fps),
 
        .o(df2io),
 
        .overflow(df2iover),
 
        .done(df2idone)
 
);
 
 
 
DFPScaleb96 udfscale1
 
(
 
        .clk(clk_g),
 
        .ce(1'b1),
 
        .a(fpd),
 
        .b(s),
 
        .o(dfscaleo)
 
);
 
 
 
`endif
 
 
always_comb
always_comb
case(ir[15:8])
case(ir[15:8])
`BRA:   takb = 1'b1;
`BRA:   takb = 1'b1;
`BSR:   takb = 1'b0;
`BSR:   takb = 1'b0;
`BHI:   takb = !cf & !zf;
`BHI:   takb = !cf & !zf;
Line 896... Line 1091...
`DBGT:  takb = ((nf & vf & !zf)|(!nf & !vf & zf));
`DBGT:  takb = ((nf & vf & !zf)|(!nf & !vf & zf));
`DBLE:  takb = (zf | (nf & !vf) | (!nf & vf));
`DBLE:  takb = (zf | (nf & !vf) | (!nf & vf));
default:        takb = 1'b1;
default:        takb = 1'b1;
endcase
endcase
 
 
 
`ifdef SUPPORT_DECFLT
 
always_comb
 
case(ir[5:0])
 
6'b000001:      ftakb =  fzf;   // EQ
 
6'b001110:      ftakb = !fzf;   // NE
 
6'b010010:      ftakb = !fnanf && !fzf && !fvf && !fnf; // GT
 
6'b011101:      ftakb = fnanf || fzf || fnf;    // NGT
 
6'b010011:      ftakb = fzf || (!fnanf && !fvf && !fnf);        // GE
 
6'b011100:      ftakb = fnanf || (fnf && !fzf);         // NGE
 
6'b010100:      ftakb = fnf && (!fnanf && !fvf && !fzf);   // LT
 
6'b011011:      ftakb = fnanf || (fzf || !fnf); // NLT
 
6'b010101:      ftakb = fzf || (fnf && !fnanf);   // LE
 
6'b011010:      ftakb = fnanf || (!fnf && !fvf && !fzf);        // NLE
 
6'b010110:      ftakb = !fnanf && !fvf && !fzf;        // GL
 
6'b011001:      ftakb = fnanf || fzf;   // NGL
 
6'b010111:      ftakb = !fnanf; // GLE
 
6'b011000:      ftakb = fnanf;  // NGLE
 
 
 
6'b000010:      ftakb = !fnanf && !fzf && !fvf && !fnf; // OGT
 
6'b001101:      ftakb = fnanf || fzf || fnf;    // ULE
 
6'b000011:      ftakb = fzf || (!fnanf && !fvf && !fnf);        // OGE
 
6'b001100:      ftakb = fnanf || (fnf && !fzf); // ULT
 
6'b000100:      ftakb = fnf && (!fnanf && !fvf && !fzf);   // OLT
 
6'b001011:      ftakb = fnanf || fzf || fnf;    // UGE
 
6'b000101:      ftakb = fzf || (fnf && !fnanf);   // OLE
 
6'b001010:      ftakb = fnanf || (!fnf && !fvf && !fzf); // UGT
 
6'b000110:      ftakb = !fnanf && !fvf && !fzf;        // OGL
 
6'b001001:      ftakb = fnanf || fzf;   // UEQ
 
6'b000111:      ftakb = !fnanf;
 
6'b001000:      ftakb = fnanf;
 
 
 
6'b000000:      ftakb = 1'b0;   // F
 
6'b001111:      ftakb = 1'b1;   // T
 
6'b010000:      ftakb = 1'b0;   // SF
 
6'b011111:      ftakb = 1'b1;   // ST
 
6'b010001:      ftakb = fzf;    // SEQ
 
6'b011110:      ftakb = !fzf;   // SNE
 
endcase
 
`endif
 
 
`ifdef BIG_ENDIAN
`ifdef BIG_ENDIAN
wire [15:0] iri = pc[1] ? {dat_i[23:16],dat_i[31:24]} : {dat_i[7:0],dat_i[15:8]};
wire [15:0] iri = pc[1] ? {dat_i[23:16],dat_i[31:24]} : {dat_i[7:0],dat_i[15:8]};
`else
`else
wire [15:0] iri = pc[1] ? dat_i[31:16] : dat_i[15:0];
wire [15:0] iri = pc[1] ? dat_i[31:16] : dat_i[15:0];
`endif
`endif
Line 918... Line 1153...
        adr_o <= 32'd0;
        adr_o <= 32'd0;
        dat_o <= 32'd0;
        dat_o <= 32'd0;
        rfwrB <= 1'b0;
        rfwrB <= 1'b0;
        rfwrW <= 1'b0;
        rfwrW <= 1'b0;
        rfwrL <= 1'b0;
        rfwrL <= 1'b0;
 
        rfwrF <= 1'b0;
        zf <= 1'b0;
        zf <= 1'b0;
        nf <= 1'b0;
        nf <= 1'b0;
        cf <= 1'b0;
        cf <= 1'b0;
        vf <= 1'b0;
        vf <= 1'b0;
        xf <= 1'b0;
        xf <= 1'b0;
        im <= 3'b111;
        im <= 3'b111;
        sf <= 1'b1;
        sf <= 1'b1;
        tf <= 1'b0;
        tf <= 1'b0;
 
        fnanf <= 1'b0;
 
        fzf <= 1'b0;
 
        fnf <= 1'b0;
 
        fvf <= 1'b0;
        goto (RESET);
        goto (RESET);
        rstate <= RESET;
        rstate <= RESET;
        prev_nmi <= 1'b0;
        prev_nmi <= 1'b0;
        pe_nmi <= 1'b0;
        pe_nmi <= 1'b0;
  tick <= 32'd0;
  tick <= 32'd0;
Line 939... Line 1179...
        MMMRRR <= 1'b0;
        MMMRRR <= 1'b0;
        rtr <= 1'b0;
        rtr <= 1'b0;
        bsr <= 1'b0;
        bsr <= 1'b0;
        lea <= 1'b0;
        lea <= 1'b0;
        divs <= 1'b0;
        divs <= 1'b0;
 
        fsub <= 1'b0;
        bcdsub <= 1'b0;
        bcdsub <= 1'b0;
        bcdneg <= 1'b0;
        bcdneg <= 1'b0;
        icnt <= 'd0;
        icnt <= 'd0;
        is_bus_err <= 1'b0;
        is_bus_err <= 1'b0;
        is_adr_err <= 1'b0;
        is_adr_err <= 1'b0;
Line 975... Line 1216...
 
 
// Register file update
// Register file update
rfwrB <= 1'b0;
rfwrB <= 1'b0;
rfwrW <= 1'b0;
rfwrW <= 1'b0;
rfwrL <= 1'b0;
rfwrL <= 1'b0;
 
rfwrF <= 1'b0;
if (rfwrL) begin
if (rfwrL) begin
  case(Rt)
  case(Rt)
  4'd0:   d0 <= resL[31:0];
  4'd0:   d0 <= resL[31:0];
  4'd1:   d1 <= resL[31:0];
  4'd1:   d1 <= resL[31:0];
  4'd2:   d2 <= resL[31:0];
  4'd2:   d2 <= resL[31:0];
Line 1027... Line 1269...
  4'd5:   d5[7:0] <= resB[7:0];
  4'd5:   d5[7:0] <= resB[7:0];
  4'd6:   d6[7:0] <= resB[7:0];
  4'd6:   d6[7:0] <= resB[7:0];
  4'd7:   d7[7:0] <= resB[7:0];
  4'd7:   d7[7:0] <= resB[7:0];
  default:    ;
  default:    ;
  endcase
  endcase
 
`ifdef SUPPORT_DECFLT
 
 if (rfwrF && DECFLT)
 
        case(Rt)
 
        4'd0:   fp0 <= resF;
 
        4'd1:   fp1 <= resF;
 
        4'd2:   fp2 <= resF;
 
        4'd3:   fp3 <= resF;
 
        4'd4:   fp4 <= resF;
 
        4'd5:   fp5 <= resF;
 
        4'd6:   fp6 <= resF;
 
        4'd7:   fp7 <= resF;
 
        default:        ;
 
        endcase
 
`endif
 
 
case(state)
case(state)
 
 
IFETCH:
IFETCH:
        begin
        begin
Line 1535... Line 1791...
                flag_update <= FU_NONE;
                flag_update <= FU_NONE;
                MMMRRR <= 1'b0;
                MMMRRR <= 1'b0;
                rtr <= 1'b0;
                rtr <= 1'b0;
                bsr <= 1'b0;
                bsr <= 1'b0;
                lea <= 1'b0;
                lea <= 1'b0;
 
                fsub <= 1'b0;
                bcdsub <= 1'b0;
                bcdsub <= 1'b0;
                bcdneg <= 1'b0;
                bcdneg <= 1'b0;
                is_illegal <= 1'b0;
                is_illegal <= 1'b0;
                use_sfc <= 1'b0;
                use_sfc <= 1'b0;
                use_dfc <= 1'b0;
                use_dfc <= 1'b0;
 
                fpcnt <= 'd0;
                if (!cyc_o) begin
                if (!cyc_o) begin
                        is_nmi <= 1'b0;
                        is_nmi <= 1'b0;
                        is_irq <= 1'b0;
                        is_irq <= 1'b0;
                        /*
                        /*
                        if (pe_nmi) begin
                        if (pe_nmi) begin
Line 1586... Line 1844...
                fc_o <= {sf,2'b10};
                fc_o <= {sf,2'b10};
                cyc_o <= 1'b1;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'b1111;
                sel_o <= 4'b1111;
                adr_o <= pc;
                adr_o <= pc;
 
                ext_ir <= 1'b1;
                goto (IFETCH2);
                goto (IFETCH2);
        end
        end
        else if (ack_i) begin
        else if (ack_i) begin
                cyc_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 2'b00;
                sel_o <= 2'b00;
                ext_ir <= 1'b1;
                ext_ir <= 1'b1;
                ir2 <= iri;
                ir2 <= iri;
 
                FLTSRC <= iri[12:10];
 
                FLTDST <= iri[ 9: 7];
                goto (DECODE);
                goto (DECODE);
        end
        end
 
 
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
Line 2319... Line 2580...
                                d <= rfoDnn;
                                d <= rfoDnn;
                        end
                        end
                end
                end
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
 
//-----------------------------------------------------------------------------
 
//-----------------------------------------------------------------------------
  5'hF:
  5'hF:
    begin
        if (ir[11:9]==3'b001)
 
                        if (ir[8:7]==2'b01) begin
 
                                if (ir[6])
 
                                        call(FETCH_IMM32,FBCC);
 
                                else
 
                                        call(FETCH_IMM16,FBCC);
 
                        end
 
                        else
 
                        goto (IFETCH2);
 
                else begin
                isr <= srx;
                isr <= srx;
                tf <= 1'b0;
                tf <= 1'b0;
                sf <= 1'b1;
                sf <= 1'b1;
        vecno <= `LINE15_VEC;
        vecno <= `LINE15_VEC;
        goto (TRAP3);
        goto (TRAP3);
Line 2347... Line 2619...
                                                goto (BCD2BIN1);
                                                goto (BCD2BIN1);
                                        end
                                        end
                                default:        tIllegal();
                                default:        tIllegal();
                                endcase
                                endcase
                        end
                        end
 
                        else
 
                                tIllegal();
 
                end
 
//-----------------------------------------------------------------------------
 
//-----------------------------------------------------------------------------
 
`ifdef SUPPORT_DECFLT
 
        5'h1F:
 
                begin
 
                        ext_ir <= 1'b0;
 
                        if (ir[11:9]==3'b001) begin
 
                                casez(ir2[15:8])
 
                                8'h6?,8'h7?:    // FMOVE to memory
 
                                        begin
 
                                                if (ir2[12:10]==3'b000) begin
 
                                                        fps <= rfoFpdst;
 
                                                        goto (DF2I1);
 
                                                end
 
                                                else begin
 
                                                        fpd <= rfoFpdst;
 
                                                        fs_data(mmm,rrr,STORE_HEXI1,D);
 
                                                end
 
                                        end
 
                                8'h??:
 
                                        case(ir2[6:0])
 
                                        7'b0000000:     // FMOVE
 
                                                if (ir2[14]) begin      // RM
 
                                                        push(FMOVE);
 
                                                        if (ir2[12:10]==3'b000)
 
                                                                fs_data(mmm,rrr,FETCH_LWORD,S);
 
                                                        else
 
                                                                fs_data(mmm,rrr,FETCH_HEXI1,S);
 
                                                end
 
                                                else begin
 
                                                        fps <= rfoFpsrc;
 
                                                        goto(FMOVE);
 
                                                end
 
                                        7'b0100000:     // FDIV
 
                                                if (ir2[14]) begin      // RM
 
                                                        fpd <= rfoFpdst;
 
                                                        push(FDIV1);
 
                                                        fs_data(mmm,rrr,FETCH_HEXI1,S);
 
                                                end
 
                                                else begin
 
                                                        fpd <= rfoFpdst;
 
                                                        fps <= rfoFpsrc;
 
                                                        goto(FDIV1);
 
                                                end
 
                                        7'b0100010:     // FADD
 
                                                if (ir2[14]) begin      // RM
 
                                                        fpd <= rfoFpdst;
 
                                                        push(FADD);
 
                                                        fs_data(mmm,rrr,FETCH_HEXI1,S);
 
                                                end
 
                                                else begin
 
                                                        fpd <= rfoFpdst;
 
                                                        fps <= rfoFpsrc;
 
                                                        goto(FADD);
 
                                                end
 
                                        7'b0100011:     // FMUL
 
                                                if (ir2[14]) begin      // RM
 
                                                        fpd <= rfoFpdst;
 
                                                        push(FMUL1);
 
                                                        fs_data(mmm,rrr,FETCH_HEXI1,S);
 
                                                end
 
                                                else begin
 
                                                        fpd <= rfoFpdst;
 
                                                        fps <= rfoFpsrc;
 
                                                        goto(FMUL1);
 
                                                end
 
                                        7'b0101000:     // FSUB
 
                                                if (ir2[14]) begin      // RM
 
                                                        fsub <= 1'b1;
 
                                                        fpd <= rfoFpdst;
 
                                                        push(FADD);
 
                                                        fs_data(mmm,rrr,FETCH_HEXI1,S);
 
                                                end
 
                                                else begin
 
                                                        fsub <= 1'b1;
 
                                                        fpd <= rfoFpdst;
 
                                                        fps <= rfoFpsrc;
 
                                                        goto(FADD);
 
                                                end
 
                                        7'b0011010:     // FNEG
 
                                                if (ir2[14]) begin      // RM
 
                                                        push(FNEG);
 
                                                        fs_data(mmm,rrr,FETCH_HEXI1,S);
 
                                                end
 
                                                else begin
 
                                                        fps <= rfoFpsrc;
 
                                                        goto(FNEG);
 
                                                end
 
                                        7'b0111000:     // FCMP
 
                                                if (ir2[14]) begin      // RM
 
                                                        fpd <= rfoFpdst;
 
                                                        push(FCMP);
 
                                                        fs_data(mmm,rrr,FETCH_HEXI1,S);
 
                                                end
 
                                                else begin
 
                                                        fpd <= rfoFpdst;
 
                                                        fps <= rfoFpsrc;
 
                                                        goto(FCMP);
 
                                                end
 
                                        7'b0111010:     // FTST
 
                                                if (ir2[14]) begin
 
                                                        push (FTST);
 
                                                        fs_data(mmm,rrr,FETCH_HEXI1,S);
 
                                                end
 
                                                else begin
 
                                                        fnf <= rfoFpsrc[95];
 
                                                        fzf <= rfoFpsrc[94:0]=='d0;
 
                                                        ret();
 
                                                end
 
                                        7'b0100110:     // FSCALE
 
                                                if (ir2[14]) begin      // RM
 
                                                        fpd <= rfoFpdst;
 
                                                        push(FSCALE);
 
                                                        case(ir2[12:10])
 
                                                        3'b000: fs_data(mmm,rrr,FETCH_LWORD,S);
 
                                                        3'b100: fs_data(mmm,rrr,FETCH_WORD,S);
 
                                                        3'b110: fs_data(mmm,rrr,FETCH_BYTE,S);
 
                                                        default:        fs_data(mmm,rrr,FETCH_LWORD,S);
 
                                                        endcase
 
                                                end
 
                                                else begin
 
                                                        fpd <= rfoFpdst;
 
                                                        push(FSCALE);
 
                                                        fs_data(3'b000,FLTSRC,FETCH_LWORD,S);
 
                                                        goto(FSCALE);
 
                                                end
 
/*
 
                                        7'b0011011:     // FGETEXP2
 
                                                begin
 
                                                        resL <= {18'd0,fpsu.exp};
 
                                                        rfwrL <= 1'b1;
 
                                                        Rt <= {1'b0,rrr};
 
                                                        ret();
 
                                                end
 
*/
 
/*
 
                                        7'b0011100:     // FCOPY
 
                                                begin
 
                                                        fps <= rfoFpsrc;
 
                                                        goto (FCOPYEXP);
 
                                                end
 
*/
 
                                        default:
 
                                                tIllegal();
 
                                        endcase
 
                                default:
 
                                        tIllegal();
 
                                endcase
 
                        end
 
                        else
 
                                tIllegal();
                end
                end
 
`endif
        default: tIllegal();
        default: tIllegal();
        endcase
        endcase
        end
        end
 
 
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
Line 4054... Line 4481...
                sel_o <= 4'b00;
                sel_o <= 4'b00;
                if (ea[1]) begin
                if (ea[1]) begin
`ifdef BIG_ENDIAN
`ifdef BIG_ENDIAN
      if (ds==D)
      if (ds==D)
        d[31:16] <= {dat_i[23:16],dat_i[31:24]};
        d[31:16] <= {dat_i[23:16],dat_i[31:24]};
      else
      else begin
        s[31:16] <= {dat_i[23:16],dat_i[31:24]};
        s[31:16] <= {dat_i[23:16],dat_i[31:24]};
 
        fps[31:16] <= {dat_i[23:16],dat_i[31:24]};
 
      end
`else
`else
      if (ds==D)
      if (ds==D)
        d[15:0] <= dat_i[31:16];
        d[15:0] <= dat_i[31:16];
      else
      else begin
        s[15:0] <= dat_i[31:16];
        s[15:0] <= dat_i[31:16];
 
        fps[15:0] <= dat_i[31:16];
 
      end
`endif
`endif
                goto (FETCH_LWORDa);
                goto (FETCH_LWORDa);
    end
    end
    else begin
    else begin
      cyc_o <= `LOW;
      cyc_o <= `LOW;
`ifdef BIG_ENDIAN
`ifdef BIG_ENDIAN
      if (ds==D)
      if (ds==D)
          d <= rbo(dat_i);
          d <= rbo(dat_i);
      else
      else begin
          s <= rbo(dat_i);
          s <= rbo(dat_i);
 
        fps <= rbo(dat_i);
 
      end
`else
`else
      if (ds==D)
      if (ds==D)
          d <= dat_i;
          d <= dat_i;
      else
      else begin
          s <= dat_i;
          s <= dat_i;
 
        fps <= dat_i;
 
      end
`endif
`endif
      ret();
      ret();
    end
    end
        end
        end
FETCH_LWORDa:
FETCH_LWORDa:
Line 4094... Line 4529...
                stb_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'b00;
                sel_o <= 4'b00;
`ifdef BIG_ENDIAN
`ifdef BIG_ENDIAN
                if (ds==D)
                if (ds==D)
                        d[15:0] <= {dat_i[7:0],dat_i[15:8]};
                        d[15:0] <= {dat_i[7:0],dat_i[15:8]};
                else
                else begin
                        s[15:0] <= {dat_i[7:0],dat_i[15:8]};
                        s[15:0] <= {dat_i[7:0],dat_i[15:8]};
 
                        fps[15:0] <= {dat_i[7:0],dat_i[15:8]};
 
                end
`else
`else
                if (ds==D)
                if (ds==D)
                        d[31:16] <= dat_i[15:0];
                        d[31:16] <= dat_i[15:0];
                else
                else begin
                        s[31:16] <= dat_i[15:0];
                        s[31:16] <= dat_i[15:0];
 
                        fps[31:16] <= dat_i[15:0];
 
                end
`endif
`endif
                ret();
                ret();
        end
        end
 
 
 
`ifdef SUPPORT_DECFLT
 
/*
 
FETCH_HEXI1:
 
        if (!cyc_o) begin
 
                fc_o <= {sf,2'b01};
 
                cyc_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                sel_o <= 4'b1111;
 
                adr_o <= ea;
 
        end
 
        else if (ack_i) begin
 
`ifdef BIG_ENDIAN
 
                if (ds==S)
 
                        fps[127:96] <= rbo(dat_i);
 
                else
 
                        fpd[127:96] <= rbo(dat_i);
 
`else
 
                if (ds==S)
 
                        fps[31:0] <= dat_i;
 
                else
 
                        fpd[31:0] <= dat_i;
 
`endif
 
                stb_o <= 1'b0;
 
                goto (FETCH_HEXI2);
 
        end
 
*/
 
FETCH_HEXI1:
 
        if (!stb_o) begin
 
                fc_o <= {sf,2'b01};
 
                cyc_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                sel_o <= 4'b1111;
 
                adr_o <= ea + 4'd0;
 
        end
 
        else if (ack_i) begin
 
`ifdef BIG_ENDIAN
 
                if (ds==S)
 
                        fps[95:64] <= rbo(dat_i);
 
                else
 
                        fpd[95:64] <= rbo(dat_i);
 
`else
 
                if (ds==S)
 
                        fps[63:32] <= dat_i;
 
                else
 
                        fpd[63:32] <= dat_i;
 
`endif
 
                stb_o <= 1'b0;
 
                goto (FETCH_HEXI3);
 
        end
 
FETCH_HEXI3:
 
        if (!stb_o) begin
 
                stb_o <= 1'b1;
 
                adr_o <= ea + 4'd4;
 
        end
 
        else if (ack_i) begin
 
`ifdef BIG_ENDIAN
 
                if (ds==S)
 
                        fps[63:32] <= rbo(dat_i);
 
                else
 
                        fpd[63:32] <= rbo(dat_i);
 
`else
 
                if (ds==S)
 
                        fps[95:64] <= dat_i;
 
                else
 
                        fpd[95:64] <= dat_i;
 
`endif
 
                stb_o <= 1'b0;
 
                goto (FETCH_HEXI4);
 
        end
 
FETCH_HEXI4:
 
        if (!stb_o) begin
 
                stb_o <= 1'b1;
 
                adr_o <= ea + 4'd8;
 
        end
 
        else if (ack_i) begin
 
`ifdef BIG_ENDIAN
 
                if (ds==S)
 
                        fps[31:0] <= rbo(dat_i);
 
                else
 
                        fpd[31:0] <= rbo(dat_i);
 
`else
 
                if (ds==S)
 
                        fps[127:96] <= dat_i;
 
                else
 
                        fpd[127:96] <= dat_i;
 
`endif
 
                cyc_o <= 1'b0;
 
                stb_o <= 1'b0;
 
                sel_o <= 4'b0000;
 
                ret();
 
        end
 
 
 
/*
 
STORE_HEXI1:
 
        if (!cyc_o) begin
 
                fc_o <= {sf,2'b01};
 
                cyc_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                we_o <= 1'b1;
 
                sel_o <= 4'b1111;
 
                adr_o <= ea;
 
`ifdef BIG_ENDIAN
 
                dat_o <= rbo(fpd[127:96]);
 
`else
 
                dat_o <= fpd[31:0];
 
`endif
 
        end
 
        else if (ack_i) begin
 
                stb_o <= 1'b0;
 
                goto (STORE_HEXI2);
 
        end
 
*/
 
STORE_HEXI1:
 
        if (!stb_o) begin
 
                fc_o <= {sf,2'b01};
 
                cyc_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                we_o <= 1'b1;
 
                sel_o <= 4'b1111;
 
                adr_o <= ea + 4'd0;
 
`ifdef BIG_ENDIAN
 
                dat_o <= rbo(fpd[95:64]);
 
`else
 
                dat_o <= fpd[63:32];
 
`endif
 
        end
 
        else if (ack_i) begin
 
                stb_o <= 1'b0;
 
                goto (STORE_HEXI3);
 
        end
 
STORE_HEXI3:
 
        if (!stb_o) begin
 
                stb_o <= 1'b1;
 
                adr_o <= ea + 4'd4;
 
`ifdef BIG_ENDIAN
 
                dat_o <= rbo(fpd[63:32]);
 
`else
 
                dat_o <= fpd[95:64];
 
`endif
 
        end
 
        else if (ack_i) begin
 
                stb_o <= 1'b0;
 
                goto (STORE_HEXI4);
 
        end
 
STORE_HEXI4:
 
        if (!stb_o) begin
 
                stb_o <= 1'b1;
 
                adr_o <= ea + 4'd8;
 
`ifdef BIG_ENDIAN
 
                dat_o <= rbo(fpd[31:0]);
 
`else
 
                dat_o <= fpd[127:96];
 
`endif
 
        end
 
        else if (ack_i) begin
 
                cyc_o <= 1'b0;
 
                stb_o <= 1'b0;
 
                we_o <= 1'b0;
 
                sel_o <= 4'b0000;
 
                ret();
 
        end
 
`endif
 
 
STORE_BYTE:
STORE_BYTE:
        if (!cyc_o) begin
        if (!cyc_o) begin
                if (use_sfc)
                if (use_sfc)
                        fc_o <= sfc[2:0];
                        fc_o <= sfc[2:0];
Line 5496... Line 6097...
                resL <= resL2;
                resL <= resL2;
                rfwrL <= 1'b1;
                rfwrL <= 1'b1;
                Rt <= {1'b0,rrr};
                Rt <= {1'b0,rrr};
                ret();
                ret();
        end
        end
 
`ifdef SUPPORT_DECFLT
 
FADD:
 
        begin
 
                fpcnt <= fpcnt + 2'd1;
 
                if (fpcnt==8'd50) begin
 
                        if (DECFLT) begin
 
                                fzf <= dfaddsubo[94:0]==95'd0;
 
                                fnf <= dfaddsubo[95];
 
                                fvf <= dfaddsubo[94:90]==5'b11110;
 
                                fnanf <= dfaddsubo[94:90]==5'b11111;
 
                                resF <= dfaddsubo;
 
                                Rt <= {1'b0,FLTDST};
 
                                rfwrF <= 1'b1;
 
                        end
 
                        ret();
 
                end
 
        end
 
FSCALE:
 
        begin
 
                fpcnt <= fpcnt + 2'd1;
 
                if (fpcnt==8'd3) begin
 
                        if (DECFLT) begin
 
                                fzf <= dfscaleo[94:0]==95'd0;
 
                                fnf <= dfscaleo[95];
 
                                fvf <= dfscaleo[94:90]==5'b11110;
 
                                fnanf <= dfscaleo[94:90]==5'b11111;
 
                                resF <= dfscaleo;
 
                                Rt <= {1'b0,FLTDST};
 
                                rfwrF <= 1'b1;
 
                        end
 
                        ret();
 
                end
 
        end
 
FNEG:
 
        begin
 
                if (DECFLT) begin
 
                        resF <= {~fps[95],fps[94:0]};
 
                        fzf <= fps[94:0]==95'd0;
 
                        fnf <= ~fps[95];
 
                        Rt <= {1'b0,FLTDST};
 
                        rfwrF <= 1'b1;
 
                end
 
                ret();
 
        end
 
FMUL1:
 
        goto (FMUL2);
 
FMUL2:
 
        if (DECFLT) begin
 
                if (dfmuldone) begin
 
                        fzf <= dfmulo[94:0]==95'd0;
 
                        fnf <= dfmulo[95];
 
                        fvf <= dfmulo[94:90]==5'b11110;
 
                        fnanf <= dfmulo[94:90]==5'b11111;
 
                        resF <= dfmulo;
 
                        Rt <= {1'b0,FLTDST};
 
                        rfwrF <= 1'b1;
 
                        ret();
 
                end
 
        end
 
        else
 
                ret();
 
FDIV1:
 
        goto (FDIV2);
 
FDIV2:
 
        if (dfdivdone) begin
 
                if (DECFLT) begin
 
                        fzf <= dfdivo[94:0]==95'd0;
 
                        fnf <= dfdivo[95];
 
                        fvf <= dfdivo[94:90]==5'b11110;
 
                        fnanf <= dfdivo[94:90]==5'b11111;
 
                        resF <= dfdivo;
 
                        Rt <= {1'b0,FLTDST};
 
                        rfwrF <= 1'b1;
 
                end
 
                ret();
 
        end
 
FCMP:
 
        begin
 
                if (DECFLT) begin
 
                        fzf <= dfcmpo[0];
 
                        fnf <= dfcmpo[1];
 
                        fvf <= 1'b0;
 
                        fnanf <= dfcmpo[4];
 
                end
 
                ret();
 
        end
 
FMOVE:
 
        begin
 
                if (DECFLT) begin
 
                        if (ir2[12:10]==3'b000) begin
 
                                fps <= {64'd0,s};
 
                                goto (I2DF1);
 
                        end
 
                        else begin
 
                                resF <= fps[95:0];
 
                                fzf <= fps[94:0]==95'd0;
 
                                fnf <= fps[95];
 
                                Rt <= {1'b0,FLTDST};
 
                                rfwrF <= 1'b1;
 
                                ret();
 
                        end
 
                end
 
                else
 
                        ret();
 
        end
 
I2DF1:
 
        goto (I2DF2);
 
I2DF2:
 
        begin
 
                if (DECFLT) begin
 
                        if (i2dfdone) begin
 
                                resF <= i2dfo;
 
                                fzf <= i2dfo[94:0]==95'd0;
 
                                fnf <= i2dfo[95];
 
                                Rt <= {1'b0,FLTDST};
 
                                rfwrF <= 1'b1;
 
                                ret();
 
                        end
 
                end
 
                else
 
                        ret();
 
        end
 
DF2I1:
 
        goto (DF2I2);
 
DF2I2:
 
        begin
 
                if (DECFLT) begin
 
                        if (df2idone) begin
 
                                resF <= df2io;
 
                                resL <= df2io;
 
                                fzf <= df2io[94:0]==95'd0;
 
                                fnf <= df2io[95];
 
                                fvf <= df2iover;
 
                                Rt <= {1'b0,FLTDST};
 
                                rfwrL <= 1'b1;
 
                                ret();
 
                        end
 
                end
 
                else
 
                        ret();
 
        end
 
FTST:
 
        begin
 
                fnf <= fps[95];
 
                fzf <= fps[94:0]=='d0;
 
                ret();
 
        end
 
FBCC:
 
        begin
 
                if (ftakb)
 
                        pc <= opc + imm;
 
                ret();
 
        end
 
/*
 
FCOPYEXP:
 
        begin
 
                resF <= fpdp;
 
                rfwrF <= 1'b1;
 
                Rt <= {1'b0,FLTDST};
 
                ret();
 
        end
 
*/
 
`endif
 
 
default:
default:
        goto(RESET);
        goto(RESET);
endcase
endcase
 
 
        // Bus error: abort current cycle and trap.
        // Bus error: abort current cycle and trap.
Line 5542... Line 6307...
begin
begin
        ds <= dsi;
        ds <= dsi;
        case(mmm)
        case(mmm)
        3'd0:   begin
        3'd0:   begin
                                if (dsi==D)
                                if (dsi==D)
                                        d <= MMMRRR ? (mmm[0] ? rfoAna : rfoDn) : rfob;
                                        d <= MMMRRR ? rfoDn : rfob;
                                else
                                else begin
                                        s <= MMMRRR ? (mmm[0] ? rfoAna : rfoDn) : rfob;
                                        s <= MMMRRR ? rfoDn : rfob;
 
                                        fps <= MMMRRR ? rfoDn : rfob;
 
                                end
                                case(size_state)
                                case(size_state)
                                STORE_LWORD:
                                STORE_LWORD:
                                        begin
                                        begin
                                                Rt <= {mmm[0],rrr};
                                                Rt <= {mmm[0],rrr};
                                                rfwrL <= 1'b1;
                                                rfwrL <= 1'b1;
Line 5604... Line 6371...
                                end
                                end
                                case(size_state)
                                case(size_state)
                                LFETCH_BYTE,FETCH_BYTE,STORE_BYTE,USTORE_BYTE:  resL <= (MMMRRR ? rfoAna : rfoAn) + 4'd1;
                                LFETCH_BYTE,FETCH_BYTE,STORE_BYTE,USTORE_BYTE:  resL <= (MMMRRR ? rfoAna : rfoAn) + 4'd1;
                                FETCH_WORD,STORE_WORD:  resL <= (MMMRRR ? rfoAna : rfoAn) + 4'd2;
                                FETCH_WORD,STORE_WORD:  resL <= (MMMRRR ? rfoAna : rfoAn) + 4'd2;
                                FETCH_LWORD,STORE_LWORD:        resL <= (MMMRRR ? rfoAna : rfoAn) + 4'd4;
                                FETCH_LWORD,STORE_LWORD:        resL <= (MMMRRR ? rfoAna : rfoAn) + 4'd4;
 
`ifdef SUPPORT_DECFLT
 
                                FETCH_HEXI1,STORE_HEXI1: resL <= (MMMRRR ? rfoAna : rfoAn) + 5'd12;
 
`endif
                                default:        ;
                                default:        ;
                                endcase
                                endcase
                                goto(size_state);
                                goto(size_state);
                        end
                        end
        3'd4:   begin   // -(An)
        3'd4:   begin   // -(An)
Line 5617... Line 6387...
                                end
                                end
                                case(size_state)
                                case(size_state)
                                FETCH_NOP_BYTE,LFETCH_BYTE,FETCH_BYTE,STORE_BYTE,USTORE_BYTE:   ea <= (MMMRRR ? rfoAna : rfoAn) - 4'd1;
                                FETCH_NOP_BYTE,LFETCH_BYTE,FETCH_BYTE,STORE_BYTE,USTORE_BYTE:   ea <= (MMMRRR ? rfoAna : rfoAn) - 4'd1;
                                FETCH_NOP_WORD,FETCH_WORD,STORE_WORD:   ea <= (MMMRRR ? rfoAna : rfoAn) - 4'd2;
                                FETCH_NOP_WORD,FETCH_WORD,STORE_WORD:   ea <= (MMMRRR ? rfoAna : rfoAn) - 4'd2;
                                FETCH_NOP_LWORD,FETCH_LWORD,STORE_LWORD:        ea <= (MMMRRR ? rfoAna : rfoAn) - 4'd4;
                                FETCH_NOP_LWORD,FETCH_LWORD,STORE_LWORD:        ea <= (MMMRRR ? rfoAna : rfoAn) - 4'd4;
 
`ifdef SUPPORT_DECFLT
 
                                FETCH_HEXI1,STORE_HEXI1: ea <= (MMMRRR ? rfoAna : rfoAn) - 5'd12;
 
`endif
                                default:        ;
                                default:        ;
                                endcase
                                endcase
                                case(size_state)
                                case(size_state)
                                LFETCH_BYTE,FETCH_BYTE,STORE_BYTE,USTORE_BYTE:  resL <= (MMMRRR ? rfoAna : rfoAn) - 4'd1;
                                LFETCH_BYTE,FETCH_BYTE,STORE_BYTE,USTORE_BYTE:  resL <= (MMMRRR ? rfoAna : rfoAn) - 4'd1;
                                FETCH_WORD,STORE_WORD:  resL <= (MMMRRR ? rfoAna : rfoAn) - 4'd2;
                                FETCH_WORD,STORE_WORD:  resL <= (MMMRRR ? rfoAna : rfoAn) - 4'd2;
                                FETCH_LWORD,STORE_LWORD:        resL <= (MMMRRR ? rfoAna : rfoAn) - 4'd4;
                                FETCH_LWORD,STORE_LWORD:        resL <= (MMMRRR ? rfoAna : rfoAn) - 4'd4;
 
`ifdef SUPPORT_DECFLT
 
                                FETCH_HEXI1,STORE_HEXI1: resL <= (MMMRRR ? rfoAna : rfoAn) - 5'd12;
 
`endif
                                default:        ;
                                default:        ;
                                endcase
                                endcase
                                goto(size_state);
                                goto(size_state);
                        end
                        end
        3'd5:   begin   // d16(An)
        3'd5:   begin   // d16(An)
Line 5677... Line 6453...
                                                        rrrx <= rrr;
                                                        rrrx <= rrr;
                                                        sz_state <= size_state;
                                                        sz_state <= size_state;
                                                        dsix <= dsi;
                                                        dsix <= dsi;
                                                        goto (FSDATA2);
                                                        goto (FSDATA2);
                                                end
                                                end
 
                                                // ToDo: add FETCH_IMM128
                                3'd4:   begin   // #i16
                                3'd4:   begin   // #i16
                                                        goto((size_state==FETCH_LWORD||size_state==FETCH_NOP_LWORD)?FETCH_IMM32:FETCH_IMM16);
                                                        goto((size_state==FETCH_LWORD||size_state==FETCH_NOP_LWORD)?FETCH_IMM32:FETCH_IMM16);
                                                end
                                                end
                                3'd5:   begin   // #i32
                                3'd5:   begin   // #i32
                                                        state <= FETCH_IMM32;
                                                        state <= FETCH_IMM32;

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