OpenCores
URL https://opencores.org/ocsvn/rf68000/rf68000/trunk

Subversion Repositories rf68000

[/] [rf68000/] [trunk/] [rtl/] [cpu/] [rf68000.sv] - Diff between revs 4 and 6

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 4 Rev 6
Line 563... Line 563... 
wire [15:0] sr = {tf,sr14,sf,sr1112,im,ccr57,xf,nf,zf,vf,cf};
 
wire [15:0] sr = {tf,sr14,sf,sr1112,im,ccr57,xf,nf,zf,vf,cf};
 
wire [31:0] srx = {sr};
 
wire [31:0] srx = {sr};
 
reg fnf,fzf,fvf,fnanf;
 
reg fnf,fzf,fvf,fnanf;
 
wire finff = fvf;
 
wire finff = fvf;
 
reg [7:0] quotient_bits;
 
reg [7:0] quotient_bits;
 
 
 
reg [2:0] quotient_bitshi;
 
reg [7:0] fpexc,fpaexc;
 
reg [7:0] fpexc,fpaexc;
 
wire [31:0] fpsr = {4'h0,fnf,fzf,fvf,fnanf,quotient_bits,fpexc,fpaexc};
 
wire [31:0] fpsr = {1'b0,quotient_bitshi,fnf,fzf,fvf,fnanf,quotient_bits,fpexc,fpaexc};
 
reg [31:0] isr;
 
reg [31:0] isr;
 
reg [3:0] ifmt;
 
reg [3:0] ifmt;
 
reg [7:0] fpcnt;
 
reg [7:0] fpcnt;
 
reg [31:0] pc;
 
reg [31:0] pc;
 
reg [31:0] opc;                 // pc for branch references
 
reg [31:0] opc;                 // pc for branch references
Line 1987... Line 1988... 
                                cf <= 1'b0;
 
                                cf <= 1'b0;
 
                                vf <= 1'b0;
 
                                vf <= 1'b0;
 
                                zf <= 1'b1;
 
                                zf <= 1'b1;
 
                                nf <= 1'b0;
 
                                nf <= 1'b0;
 
                                d <= 'd0;
 
                                d <= 'd0;
 
 
 
                                resB <= 'd0;
 
 
 
                                resW <= 'd0;
 
 
 
                                resL <= 'd0;
 
                                case(sz)
 
                                case(sz)
 
                                2'b00:  fs_data(mmm,rrr,STORE_BYTE,D);
 
                                2'b00:  fs_data(mmm,rrr,STORE_BYTE,D);
 
                                2'b01:  fs_data(mmm,rrr,STORE_WORD,D);
 
                                2'b01:  fs_data(mmm,rrr,STORE_WORD,D);
 
                                2'b10:  fs_data(mmm,rrr,STORE_LWORD,D);
 
                                2'b10:  fs_data(mmm,rrr,STORE_LWORD,D);
 
                                default:        tIllegal();
 
                                default:        tIllegal();
Line 2641... Line 2645... 
                                                else begin
 
                                                else begin
 
                                                        fpd <= rfoFpdst;
 
                                                        fpd <= rfoFpdst;
 
                                                        fs_data(mmm,rrr,STORE_HEXI1,D);
 
                                                        fs_data(mmm,rrr,STORE_HEXI1,D);
 
                                                end
 
                                                end
 
                                        end
 
                                        end
 
 
 
                                8'b10????00:    // PG 4-71
 
 
 
                                        if (ir2[13])
 
 
 
                                                case(ir2[7:0])
 
 
 
                                                8'h00:  // FMOVE
 
 
 
                                                        case(ir2[12:10])
 
 
 
                                                        3'b001: tIllegal();     // FPIAR
 
 
 
                                                        3'b010: // FPSR
 
 
 
                                                                begin
 
 
 
                                                                        d <= fpsr;
 
 
 
                                                                        fs_data(mmm,rrr,STORE_LWORD,D);
 
 
 
                                                                end
 
 
 
                                                        3'b100: tIllegal();// FPCR
 
 
 
                                                        default:        tIllegal();
 
 
 
                                                        endcase
 
 
 
                                                default:        tIllegal();
 
 
 
                                                endcase
 
 
 
                                        else
 
 
 
                                                tIllegal();
 
                                8'h??:
 
                                8'h??:
 
                                        case(ir2[6:0])
 
                                        case(ir2[6:0])
 
                                        7'b0000000:     // FMOVE
 
                                        7'b0000000:     // FMOVE
 
                                                if (ir2[14]) begin      // RM
 
                                                if (ir2[14]) begin      // RM
 
                                                        push(FMOVE);
 
                                                        push(FMOVE);
Line 6170... Line 6192... 
                        fvf <= dfdivo[94:90]==5'b11110;
 
                        fvf <= dfdivo[94:90]==5'b11110;
 
                        fnanf <= dfdivo[94:90]==5'b11111;
 
                        fnanf <= dfdivo[94:90]==5'b11111;
 
                        resF <= dfdivo;
 
                        resF <= dfdivo;
 
                        Rt <= {1'b0,FLTDST};
 
                        Rt <= {1'b0,FLTDST};
 
                        rfwrF <= 1'b1;
 
                        rfwrF <= 1'b1;
 
 
 
                        quotient_bits <= {dfdivo[95],dfdivo[6:0]};
 
 
 
                        quotient_bitshi <= {dfdivo[9:7]};
 
                end
 
                end
 
                ret();
 
                ret();
 
        end
 
        end
 
FCMP:
 
FCMP:
 
        begin
 
        begin

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.