| Line 206... |
Line 206... |
(ir[bitsPerByte+2] ? 5'd1 : 5'd0) +
|
(ir[bitsPerByte+2] ? 5'd1 : 5'd0) +
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(ir[bitsPerByte+3] ? 5'd1 : 5'd0) +
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(ir[bitsPerByte+3] ? 5'd1 : 5'd0) +
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(ir[bitsPerByte+4] ? 5'd2 : 5'd0) +
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(ir[bitsPerByte+4] ? 5'd2 : 5'd0) +
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(ir[bitsPerByte+5] ? 5'd2 : 5'd0) +
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(ir[bitsPerByte+5] ? 5'd2 : 5'd0) +
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(ir[bitsPerByte+6] ? 5'd2 : 5'd0) +
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(ir[bitsPerByte+6] ? 5'd2 : 5'd0) +
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(ir[bitsPerByte+7] ? 5'd2 : 5'd0)
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(ir[bitsPerByte+7] ? (isFar ? 5'd3 : 5'd2) : 5'd0)
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;
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;
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// cnt = 0;
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// cnt = 0;
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// if (ir[8]) cnt = cnt + 5'd1; // CC
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// if (ir[8]) cnt = cnt + 5'd1; // CC
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// if (ir[9]) cnt = cnt + md32 ? 5'd4 : 5'd1; // A
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// if (ir[9]) cnt = cnt + md32 ? 5'd4 : 5'd1; // A
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// if (ir[10]) cnt = cnt + md32 ? 5'd4 : 5'd1; // B
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// if (ir[10]) cnt = cnt + md32 ? 5'd4 : 5'd1; // B
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| Line 1046... |
Line 1046... |
waitcnt <= 6'd20;
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waitcnt <= 6'd20;
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next_state(ICACHE7);
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next_state(ICACHE7);
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end
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end
|
ICACHE7:
|
ICACHE7:
|
if (waitcnt==6'd0) begin
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if (waitcnt==6'd0) begin
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next_state(ICACHE6);
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next_state(ICACHE5);
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adr_o <= icwa;
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adr_o <= icwa;
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for (n4 = 15; n4 >= 0; n4 = n4 - 1)
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for (n4 = 15; n4 >= 0; n4 = n4 - 1)
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if (~icgot[n4] & ~outstanding[n4]) begin
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if (~icgot[n4]) begin// & ~outstanding[n4]) begin
|
cti_o <= 3'b001;
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cti_o <= 3'b001;
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cyc_o <= TRUE;
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cyc_o <= `TRUE;
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stb_o <= TRUE;
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stb_o <= `TRUE;
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adr_o[3:0] <= n4[3:0];
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adr_o[3:0] <= n4[3:0];
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outstanding[n4[3:0]] <= 1'b1;
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outstanding[n4[3:0]] <= 1'b1;
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next_state(ICACHE9);
|
next_state(ICACHE9);
|
end
|
end
|
end
|
end
|
| Line 1065... |
Line 1065... |
ICACHE9:
|
ICACHE9:
|
begin
|
begin
|
if (bto)
|
if (bto)
|
outstanding <= 16'h0;
|
outstanding <= 16'h0;
|
if (aack_i)
|
if (aack_i)
|
outstanding[adr_o[3:0]] <= 1'b0;
|
outstanding[atag_i] <= 1'b0;
|
if (ack_i|rty_i|bto) begin
|
if (ack_i|rty_i|bto) begin
|
wb_nack();
|
wb_nack();
|
waitcnt <= 6'd20;
|
waitcnt <= 6'd20;
|
next_state(ICACHE7);
|
next_state(ICACHE7);
|
end
|
end
|
| Line 2933... |
Line 2933... |
end
|
end
|
`LW_ACCB: begin
|
`LW_ACCB: begin
|
accb <= dat;
|
accb <= dat;
|
radr <= radr + 2'd1;
|
radr <= radr + 2'd1;
|
if (isRTI) begin
|
if (isRTI) begin
|
$display("loaded accb=%h from ", dat, radr);
|
$display("loaded accb=%h from %h", dat, radr);
|
ssp <= ssp + 2'd1;
|
ssp <= ssp + 2'd1;
|
next_state(PULL1);
|
next_state(PULL1);
|
end
|
end
|
else if (isPULU) begin
|
else if (isPULU) begin
|
usp <= usp + 2'd1;
|
usp <= usp + 2'd1;
|
| Line 3095... |
Line 3095... |
next_state(IFETCH);
|
next_state(IFETCH);
|
end
|
end
|
`LW_PCL: begin
|
`LW_PCL: begin
|
pc[`LOBYTE] <= dat;
|
pc[`LOBYTE] <= dat;
|
radr <= radr + 2'd1;
|
radr <= radr + 2'd1;
|
|
// If loading from the vector table in bank zero, force pc[23:16]=0
|
|
if (radr[`BYTE3]=={BPB{1'b0}} && radr[`BYTE2]=={BPB{1'b1}} && radr[7:4]==4'hF)
|
|
pc[`BYTE3] <= {BPB{1'b0}};
|
if (isRTI|isRTS|isPULS) begin
|
if (isRTI|isRTS|isPULS) begin
|
$display("loadded PCL=%h", dat);
|
$display("loadded PCL=%h", dat);
|
ssp <= ssp + 2'd1;
|
ssp <= ssp + 2'd1;
|
end
|
end
|
else if (isPULU)
|
else if (isPULU)
|
