| Line 166... |
Line 166... |
reg isRTS,isRTI,isRTF;
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reg isRTS,isRTI,isRTF;
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reg isLEA;
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reg isLEA;
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reg isRMW;
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reg isRMW;
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|
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// Data input path multiplexing
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// Data input path multiplexing
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reg [BPB-1:0] dati;
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reg [bitsPerByte-1:0] dati;
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always_comb
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always_comb
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dati = dat_i;
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dati = dat_i;
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|
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// Evaluate the branch conditional
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// Evaluate the branch conditional
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reg takb;
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reg takb;
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| Line 229... |
Line 229... |
wire isIndexed =
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wire isIndexed =
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ir12[7:4]==4'h6 || ir12[7:4]==4'hA || ir12[7:4]==4'hE ||
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ir12[7:4]==4'h6 || ir12[7:4]==4'hA || ir12[7:4]==4'hE ||
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ir12==`LEAX_NDX || ir12==`LEAY_NDX || ir12==`LEAS_NDX || ir12==`LEAU_NDX
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ir12==`LEAX_NDX || ir12==`LEAY_NDX || ir12==`LEAS_NDX || ir12==`LEAU_NDX
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;
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;
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reg isDblIndirect;
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reg isDblIndirect;
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wire isIndirect = ndxbyte[BPBM1-3] & ndxbyte[BPBM1];
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wire isIndirect = ndxbyte[bitsPerByte-4] & ndxbyte[bitsPerByte-1];
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assign ndxbyte = ir[`HIBYTE];
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assign ndxbyte = ir[`HIBYTE];
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|
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// Detect type of interrupt
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// Detect type of interrupt
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wire isINT = ir12==`INT;
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wire isINT = ir12==`INT;
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wire isRST = vect[3:0]==4'hE;
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wire isRST = vect[3:0]==4'hE;
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| Line 877... |
Line 877... |
// Outer Indexing Support
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// Outer Indexing Support
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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OUTER_INDEXING:
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OUTER_INDEXING:
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begin
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begin
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if (bitsPerByte==8) begin
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if (bitsPerByte==8) begin
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casex(ndxbyte)
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casez(ndxbyte)
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8'b0xxxxxxx: radr <= radr + ndxreg;
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8'b0???????: radr <= radr + ndxreg;
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8'b1xxx0000:
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8'b1???0000:
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begin
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begin
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radr <= radr + ndxreg;
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radr <= radr + ndxreg;
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case(ndxbyte[6:5])
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case(ndxbyte[6:5])
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2'b00: xr <= (xr + 2'd1);
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2'b00: xr <= (xr + 2'd1);
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2'b01: yr <= (yr + 2'd1);
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2'b01: yr <= (yr + 2'd1);
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2'b10: usp <= (usp + 2'd1);
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2'b10: usp <= (usp + 2'd1);
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2'b11: ssp <= (ssp + 2'd1);
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2'b11: ssp <= (ssp + 2'd1);
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endcase
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endcase
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end
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end
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8'b1xxx0001: begin
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8'b1???0001: begin
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radr <= radr + ndxreg;
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radr <= radr + ndxreg;
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case(ndxbyte[6:5])
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case(ndxbyte[6:5])
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2'b00: xr <= (xr + 2'd2);
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2'b00: xr <= (xr + 2'd2);
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2'b01: yr <= (yr + 2'd2);
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2'b01: yr <= (yr + 2'd2);
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2'b10: usp <= (usp + 2'd2);
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2'b10: usp <= (usp + 2'd2);
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2'b11: ssp <= (ssp + 2'd2);
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2'b11: ssp <= (ssp + 2'd2);
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endcase
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endcase
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end
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end
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8'b1xxx0010: radr <= radr + ndxreg;
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8'b1???0010: radr <= radr + ndxreg;
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8'b1xxx0011: radr <= radr + ndxreg;
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8'b1???0011: radr <= radr + ndxreg;
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8'b1xxx0100: radr <= radr + ndxreg;
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8'b1???0100: radr <= radr + ndxreg;
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8'b1xxx0101: radr <= radr + ndxreg;
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8'b1???0101: radr <= radr + ndxreg;
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8'b1xxx0110: radr <= radr + ndxreg;
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8'b1???0110: radr <= radr + ndxreg;
|
8'b1xxx1000: radr <= radr + ndxreg;
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8'b1???1000: radr <= radr + ndxreg;
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8'b1xxx1001: radr <= radr + ndxreg;
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8'b1???1001: radr <= radr + ndxreg;
|
8'b1xxx1010: radr <= radr + ndxreg;
|
8'b1???1010: radr <= radr + ndxreg;
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8'b1xxx1011: radr <= radr + ndxreg;
|
8'b1???1011: radr <= radr + ndxreg;
|
default: radr <= radr;
|
default: radr <= radr;
|
endcase
|
endcase
|
end
|
end
|
else if (bitsPerByte==12) begin
|
else if (bitsPerByte==12) begin
|
casex(ndxbyte)
|
casez(ndxbyte)
|
12'b0xxxxxxxxxxx: radr <= radr + ndxreg;
|
12'b0???????????: radr <= radr + ndxreg;
|
12'b1xxxx0000000:
|
12'b1????0000000:
|
begin
|
begin
|
radr <= radr + ndxreg;
|
radr <= radr + ndxreg;
|
case(ndxbyte[10:9])
|
case(ndxbyte[10:9])
|
2'b00: xr <= (xr + 2'd1);
|
2'b00: xr <= (xr + 2'd1);
|
2'b01: yr <= (yr + 2'd1);
|
2'b01: yr <= (yr + 2'd1);
|
2'b10: usp <= (usp + 2'd1);
|
2'b10: usp <= (usp + 2'd1);
|
2'b11: ssp <= (ssp + 2'd1);
|
2'b11: ssp <= (ssp + 2'd1);
|
endcase
|
endcase
|
end
|
end
|
12'b1xxxx0000001: begin
|
12'b1????0000001: begin
|
radr <= radr + ndxreg;
|
radr <= radr + ndxreg;
|
case(ndxbyte[10:9])
|
case(ndxbyte[10:9])
|
2'b00: xr <= (xr + 2'd2);
|
2'b00: xr <= (xr + 2'd2);
|
2'b01: yr <= (yr + 2'd2);
|
2'b01: yr <= (yr + 2'd2);
|
2'b10: usp <= (usp + 2'd2);
|
2'b10: usp <= (usp + 2'd2);
|
2'b11: ssp <= (ssp + 2'd2);
|
2'b11: ssp <= (ssp + 2'd2);
|
endcase
|
endcase
|
end
|
end
|
12'b1xxxx0000010: radr <= radr + ndxreg;
|
12'b1????0000010: radr <= radr + ndxreg;
|
12'b1xxxx0000011: radr <= radr + ndxreg;
|
12'b1????0000011: radr <= radr + ndxreg;
|
12'b1xxxx0000100: radr <= radr + ndxreg;
|
12'b1????0000100: radr <= radr + ndxreg;
|
12'b1xxxx0000101: radr <= radr + ndxreg;
|
12'b1????0000101: radr <= radr + ndxreg;
|
12'b1xxxx0000110: radr <= radr + ndxreg;
|
12'b1????0000110: radr <= radr + ndxreg;
|
12'b1xxxx0001000: radr <= radr + ndxreg;
|
12'b1????0001000: radr <= radr + ndxreg;
|
12'b1xxxx0001001: radr <= radr + ndxreg;
|
12'b1????0001001: radr <= radr + ndxreg;
|
12'b1xxxx0001010: radr <= radr + ndxreg;
|
12'b1????0001010: radr <= radr + ndxreg;
|
12'b1xxxx0001011: radr <= radr + ndxreg;
|
12'b1????0001011: radr <= radr + ndxreg;
|
default: radr <= radr;
|
default: radr <= radr;
|
endcase
|
endcase
|
end
|
end
|
next_state(OUTER_INDEXING2);
|
next_state(OUTER_INDEXING2);
|
end
|
end
|
| Line 1184... |
Line 1184... |
bs_o <= 1'b0;
|
bs_o <= 1'b0;
|
next_state(DECODE);
|
next_state(DECODE);
|
isFar <= `FALSE;
|
isFar <= `FALSE;
|
isOuterIndexed <= `FALSE;
|
isOuterIndexed <= `FALSE;
|
ipg <= 2'b00;
|
ipg <= 2'b00;
|
ia <= 24'd0;
|
ia <= {bitsPerByte*3{1'b0}};
|
res <= 24'd0;
|
res <= 24'd0;
|
load_what <= `LW_NOTHING;
|
load_what <= `LW_NOTHING;
|
store_what <= `SW_NOTHING;
|
store_what <= `SW_NOTHING;
|
if (nmi_edge | firq_i | irq_i)
|
if (nmi_edge | firq_i | irq_i)
|
sync_state <= `FALSE;
|
sync_state <= `FALSE;
|
| Line 1257... |
Line 1257... |
first_ifetch <= `TRUE;
|
first_ifetch <= `TRUE;
|
next_state(IFETCH); // default: move to IFETCH
|
next_state(IFETCH); // default: move to IFETCH
|
pc <= pc + 2'd1; // default: increment PC by one
|
pc <= pc + 2'd1; // default: increment PC by one
|
a <= 24'd0;
|
a <= 24'd0;
|
b <= 24'd0;
|
b <= 24'd0;
|
ia <= 24'd0;
|
ia <= {bitsPerByte * 3{1'b0}};
|
isDblIndirect <= `FALSE;//ndxbyte[11:4]==8'h8F;
|
isDblIndirect <= `FALSE;//ndxbyte[11:4]==8'h8F;
|
if (isIndexed) begin
|
if (isIndexed) begin
|
if (bitsPerByte==8) begin
|
if (bitsPerByte==8) begin
|
casez(ndxbyte)
|
casez(ndxbyte)
|
8'b1??00000:
|
8'b1??00000:
|
| Line 2829... |
Line 2829... |
bte_o <= 2'b00;
|
bte_o <= 2'b00;
|
cti_o <= 3'b001;
|
cti_o <= 3'b001;
|
bl_o <= len;
|
bl_o <= len;
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
|
we_o <= 1'b0;
|
adr_o <= adr;
|
adr_o <= adr;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
| Line 2840... |
Line 2841... |
input [`TRPBYTE] adr;
|
input [`TRPBYTE] adr;
|
begin
|
begin
|
if (!tsc) begin
|
if (!tsc) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
|
we_o <= 1'b0;
|
adr_o <= adr;
|
adr_o <= adr;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
| Line 3249... |
Line 3251... |
if (rce) rpcp16 <= pc + 5'd16;
|
if (rce) rpcp16 <= pc + 5'd16;
|
assign tag0 = {mem[rpc[11:4]],tvalid[rpc[11:4]]};
|
assign tag0 = {mem[rpc[11:4]],tvalid[rpc[11:4]]};
|
assign tag1 = {mem[rpcp16[11:4]],tvalid[rpcp16[11:4]]};
|
assign tag1 = {mem[rpcp16[11:4]],tvalid[rpcp16[11:4]]};
|
|
|
assign hit0 = tag0 == {rpc[BPB*3-1:12],1'b1};
|
assign hit0 = tag0 == {rpc[BPB*3-1:12],1'b1};
|
assign hit1 = tag1 == {rpcp16[BPB*3-1:12],1'b1};
|
// Consider a hit on port 1 if the instruction will not span onto it.
|
|
assign hit1 = tag1 == {rpcp16[BPB*3-1:12],1'b1} || rpc[3:0] < 4'h9;
|
|
|
endmodule
|
endmodule
|
|
|
