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[/] [rf6809/] [trunk/] [rtl/] [cpu/] [rf6809.sv] - Diff between revs 12 and 13

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Rev 12 Rev 13
Line 230... Line 230...
        ir12[7:4]==4'h6 || ir12[7:4]==4'hA || ir12[7:4]==4'hE ||
        ir12[7:4]==4'h6 || ir12[7:4]==4'hA || ir12[7:4]==4'hE ||
        ir12==`LEAX_NDX || ir12==`LEAY_NDX || ir12==`LEAS_NDX || ir12==`LEAU_NDX
        ir12==`LEAX_NDX || ir12==`LEAY_NDX || ir12==`LEAS_NDX || ir12==`LEAU_NDX
        ;
        ;
reg isDblIndirect;
reg isDblIndirect;
wire isIndirect = ndxbyte[bitsPerByte-4] & ndxbyte[bitsPerByte-1];
wire isIndirect = ndxbyte[bitsPerByte-4] & ndxbyte[bitsPerByte-1];
 
`ifdef TWELVEBIT
 
always_comb
 
        isOuterIndexed = ndxbyte[bitsPerByte-5] & ndxbyte[bitsPerByte-1];
 
`endif
 
 
assign ndxbyte = ir[`HIBYTE];
assign ndxbyte = ir[`HIBYTE];
 
 
// Detect type of interrupt
// Detect type of interrupt
wire isINT = ir12==`INT;
wire isINT = ir12==`INT;
wire isRST = vect[3:0]==4'hE;
wire isRST = vect[3:0]==4'hE;
Line 697... Line 702...
        sync_state <= `FALSE;
        sync_state <= `FALSE;
        wait_state <= `FALSE;
        wait_state <= `FALSE;
        md32 <= `FALSE;
        md32 <= `FALSE;
        ipg <= 2'b00;
        ipg <= 2'b00;
        isFar <= `FALSE;
        isFar <= `FALSE;
 
`ifdef EIGHTBIT
        isOuterIndexed <= `FALSE;
        isOuterIndexed <= `FALSE;
 
`endif
        dpr <= 12'h000;
        dpr <= 12'h000;
        ibufadr <= {BPB*3{1'b0}};
        ibufadr <= {BPB*3{1'b0}};
//      pc <= 24'hFFFFFE;
//      pc <= 24'hFFFFFE;
        pc <= {{BPB*3-1{1'b1}},1'b0};   // FF...FE
        pc <= {{BPB*3-1{1'b1}},1'b0};   // FF...FE
        ir <= {4{`NOP}};
        ir <= {4{`NOP}};
Line 1182... Line 1189...
        else begin
        else begin
                ba_o <= 1'b0;
                ba_o <= 1'b0;
                bs_o <= 1'b0;
                bs_o <= 1'b0;
                next_state(DECODE);
                next_state(DECODE);
                isFar <= `FALSE;
                isFar <= `FALSE;
 
`ifdef EIGHTBIT
                isOuterIndexed <= `FALSE;
                isOuterIndexed <= `FALSE;
 
`endif
                ipg <= 2'b00;
                ipg <= 2'b00;
                ia <= {bitsPerByte*3{1'b0}};
                ia <= {bitsPerByte*3{1'b0}};
                res <= 24'd0;
                res <= 24'd0;
                load_what <= `LW_NOTHING;
                load_what <= `LW_NOTHING;
                store_what <= `SW_NOTHING;
                store_what <= `SW_NOTHING;
Line 1223... Line 1232...
                                        ir <= insn;
                                        ir <= insn;
                                end
                                end
                                else begin
                                else begin
                                        ipg <= ipg;
                                        ipg <= ipg;
                                        isFar <= isFar;
                                        isFar <= isFar;
 
`ifdef EIGHTBIT
                                        isOuterIndexed <= isOuterIndexed;
                                        isOuterIndexed <= isOuterIndexed;
 
`endif
                                        next_state(ICACHE1);
                                        next_state(ICACHE1);
                                end
                                end
                        end
                        end
`ifdef SUPPORT_IBUF
`ifdef SUPPORT_IBUF
                        else begin
                        else begin
                                if (ibufhit)
                                if (ibufhit)
                                        ir <= ibuf;
                                        ir <= ibuf;
                                else begin
                                else begin
                                        ipg <= ipg;
                                        ipg <= ipg;
                                        isFar <= isFar;
                                        isFar <= isFar;
 
`ifdef EIGHTBIT
                                        isOuterIndexed <= isOuterIndexed;
                                        isOuterIndexed <= isOuterIndexed;
 
`endif
                                        next_state(IBUF1);
                                        next_state(IBUF1);
                                end
                                end
                        end
                        end
`endif
`endif
                end
                end
Line 1297... Line 1310...
                        endcase
                        endcase
                end
                end
                else if (bitsPerByte==12) begin
                else if (bitsPerByte==12) begin
                        casez(ndxbyte)
                        casez(ndxbyte)
                        12'b1??000000000:
                        12'b1??000000000:
                                if (!isOuterIndexed && ndxbyte[7]==1'b0)
                                if (!isOuterIndexed && ndxbyte[bitsPerByte-5]==1'b0)
                                        case(ndxbyte[10:9])
                                        case(ndxbyte[10:9])
                                        2'b00:  xr <= (xr + 4'd1);
                                        2'b00:  xr <= (xr + 4'd1);
                                        2'b01:  yr <= (yr + 4'd1);
                                        2'b01:  yr <= (yr + 4'd1);
                                        2'b10:  usp <= (usp + 4'd1);
                                        2'b10:  usp <= (usp + 4'd1);
                                        2'b11:  ssp <= (ssp + 4'd1);
                                        2'b11:  ssp <= (ssp + 4'd1);
                                        endcase
                                        endcase
                        12'b1??000000001:
                        12'b1??000000001:
                                if (!isOuterIndexed && ndxbyte[7]==1'b0)
                                if (!isOuterIndexed && ndxbyte[bitsPerByte-5]==1'b0)
                                        case(ndxbyte[10:9])
                                        case(ndxbyte[10:9])
                                        2'b00:  xr <= (xr + 4'd2);
                                        2'b00:  xr <= (xr + 4'd2);
                                        2'b01:  yr <= (yr + 4'd2);
                                        2'b01:  yr <= (yr + 4'd2);
                                        2'b10:  usp <= (usp + 4'd2);
                                        2'b10:  usp <= (usp + 4'd2);
                                        2'b11:  ssp <= (ssp + 4'd2);
                                        2'b11:  ssp <= (ssp + 4'd2);
Line 1390... Line 1403...
        `ABX:   res <= xr + accb;
        `ABX:   res <= xr + accb;
        `SEX: res <= {{bitsPerByte{accb[BPBM1]}},accb[`LOBYTE]};
        `SEX: res <= {{bitsPerByte{accb[BPBM1]}},accb[`LOBYTE]};
        `PG2:   begin ipg <= 2'b01; ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
        `PG2:   begin ipg <= 2'b01; ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
        `PG3:   begin ipg <= 2'b10; ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
        `PG3:   begin ipg <= 2'b10; ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
        `FAR:   begin isFar <= `TRUE;  ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
        `FAR:   begin isFar <= `TRUE;  ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
 
`ifdef EIGHTBIT
        `OUTER: begin isOuterIndexed <= `TRUE;  ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
        `OUTER: begin isOuterIndexed <= `TRUE;  ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
 
`endif
        `NEGA,`NEGB:    begin res12 <= -acc[`LOBYTE]; a <= 24'h00; b <= acc; end
        `NEGA,`NEGB:    begin res12 <= -acc[`LOBYTE]; a <= 24'h00; b <= acc; end
        `COMA,`COMB:    begin res12 <= ~acc[`LOBYTE]; end
        `COMA,`COMB:    begin res12 <= ~acc[`LOBYTE]; end
        `LSRA,`LSRB:    begin res12 <= {acc[0],1'b0,acc[BPBM1:1]}; end
        `LSRA,`LSRB:    begin res12 <= {acc[0],1'b0,acc[BPBM1:1]}; end
        `RORA,`RORB:    begin res12 <= {acc[0],cf,acc[BPBM1:1]}; end
        `RORA,`RORB:    begin res12 <= {acc[0],cf,acc[BPBM1:1]}; end
        `ASRA,`ASRB:    begin res12 <= {acc[0],acc[BPBM1],acc[BPBM1:1]}; end
        `ASRA,`ASRB:    begin res12 <= {acc[0],acc[BPBM1],acc[BPBM1:1]}; end

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