| Line 343... |
Line 343... |
13'b01???10000100: NdxAddr <= 24'd0;
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13'b01???10000100: NdxAddr <= 24'd0;
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13'b01???10000101: NdxAddr <= {{BPB*2{accb[BPBM1]}},accb};
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13'b01???10000101: NdxAddr <= {{BPB*2{accb[BPBM1]}},accb};
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13'b01???10000110: NdxAddr <= {{BPB*2{acca[BPBM1]}},acca};
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13'b01???10000110: NdxAddr <= {{BPB*2{acca[BPBM1]}},acca};
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13'b01???10001000: NdxAddr <= offset12;
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13'b01???10001000: NdxAddr <= offset12;
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13'b01???10001001: NdxAddr <= offset24;
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13'b01???10001001: NdxAddr <= offset24;
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13'b01???10001010: NdxAddr <= offset24;
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13'b01???10001010: NdxAddr <= offset36;
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13'b01???10001011: NdxAddr <= {acca,accb};
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13'b01???10001011: NdxAddr <= {acca,accb};
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13'b01???10001100: NdxAddr <= pc + offset12 + 3'd3;
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13'b01???10001100: NdxAddr <= pc + offset12 + 3'd3;
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13'b01???10001101: NdxAddr <= pc + offset24 + 3'd4;
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13'b01???10001101: NdxAddr <= pc + offset24 + 3'd4;
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13'b01???10001110: NdxAddr <= pc + offset36 + 3'd5;
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13'b01???10001110: NdxAddr <= pc + offset36 + 3'd5;
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13'b01??010001111: NdxAddr <= isFar ? offset36 : offset24;
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13'b01??010001111: NdxAddr <= isFar ? offset36 : offset24;
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| Line 412... |
Line 412... |
12'b1???00001011: insnsz <= 4'h2;
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12'b1???00001011: insnsz <= 4'h2;
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12'b1???00001100: insnsz <= 4'h3;
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12'b1???00001100: insnsz <= 4'h3;
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12'b1???00001101: insnsz <= 4'h4;
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12'b1???00001101: insnsz <= 4'h4;
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12'b1???00001110: insnsz <= 4'h5;
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12'b1???00001110: insnsz <= 4'h5;
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12'b1??000001111: insnsz <= isFar ? 4'h5 : 4'h4;
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12'b1??000001111: insnsz <= isFar ? 4'h5 : 4'h4;
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12'b1??000011111: insnsz <= 4'h4;
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12'b1??100001111: insnsz <= 4'h4;
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default: insnsz <= 4'h2;
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default: insnsz <= 4'h2;
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endcase
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endcase
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|
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// Source registers for transfer or exchange instructions.
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// Source registers for transfer or exchange instructions.
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reg [`DBLBYTE] src1,src2;
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reg [`DBLBYTE] src1,src2;
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| Line 721... |
Line 721... |
acca <= 12'h0;
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acca <= 12'h0;
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accb <= 12'h0;
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accb <= 12'h0;
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accd <= 24'h0;
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accd <= 24'h0;
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xr <= 24'h0;
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xr <= 24'h0;
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yr <= 24'h0;
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yr <= 24'h0;
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|
usppg <= 16'h0;
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usp <= 24'h0;
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usp <= 24'h0;
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ssp <= 24'h0;
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ssp <= 24'h0;
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if (halt_i) begin
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if (halt_i) begin
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ba_o <= 1'b1;
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ba_o <= 1'b1;
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bs_o <= 1'b1;
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bs_o <= 1'b1;
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| Line 776... |
Line 777... |
if (isINT | isPSHS) begin
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if (isINT | isPSHS) begin
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wadr <= (ssp - cnt);
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wadr <= (ssp - cnt);
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ssp <= (ssp - cnt);
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ssp <= (ssp - cnt);
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end
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end
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else begin // PSHU
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else begin // PSHU
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wadr <= ({usppg,8'h00} + usp - cnt);
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wadr <= ({usppg,{bitsPerByte{1'b0}}} + usp - cnt);
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usp <= (usp - cnt);
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usp <= (usp - cnt);
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end
|
end
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end
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end
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PUSH2:
|
PUSH2:
|
begin
|
begin
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| Line 1325... |
Line 1326... |
2'b00: xr <= (xr + 4'd2);
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2'b00: xr <= (xr + 4'd2);
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2'b01: yr <= (yr + 4'd2);
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2'b01: yr <= (yr + 4'd2);
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2'b10: usp <= (usp + 4'd2);
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2'b10: usp <= (usp + 4'd2);
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2'b11: ssp <= (ssp + 4'd2);
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2'b11: ssp <= (ssp + 4'd2);
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endcase
|
endcase
|
12'b1??0x0000010:
|
12'b1??0?0000010:
|
case(ndxbyte[10:9])
|
case(ndxbyte[10:9])
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2'b00: xr <= (xr - 2'd1);
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2'b00: xr <= (xr - 2'd1);
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2'b01: yr <= (yr - 2'd1);
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2'b01: yr <= (yr - 2'd1);
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2'b10: usp <= (usp - 2'd1);
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2'b10: usp <= (usp - 2'd1);
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2'b11: ssp <= (ssp - 2'd1);
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2'b11: ssp <= (ssp - 2'd1);
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endcase
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endcase
|
12'b1??0x0000011:
|
12'b1??0?0000011:
|
case(ndxbyte[10:9])
|
case(ndxbyte[10:9])
|
2'b00: xr <= (xr - 2'd2);
|
2'b00: xr <= (xr - 2'd2);
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2'b01: yr <= (yr - 2'd2);
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2'b01: yr <= (yr - 2'd2);
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2'b10: usp <= (usp - 2'd2);
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2'b10: usp <= (usp - 2'd2);
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2'b11: ssp <= (ssp - 2'd2);
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2'b11: ssp <= (ssp - 2'd2);
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| Line 1683... |
Line 1684... |
pc <= pc + 2'd2;
|
pc <= pc + 2'd2;
|
next_state(STORE1);
|
next_state(STORE1);
|
end
|
end
|
`JSR_NDX:
|
`JSR_NDX:
|
begin
|
begin
|
|
if (isFar) begin
|
|
store_what <= `SW_PC2316;
|
|
wadr <= ssp - 16'd3;
|
|
ssp <= ssp - 16'd3;
|
|
end
|
begin
|
begin
|
store_what <= `SW_PCH;
|
store_what <= `SW_PCH;
|
wadr <= ssp - 2'd2;
|
wadr <= ssp - 2'd2;
|
ssp <= ssp - 2'd2;
|
ssp <= ssp - 2'd2;
|
end
|
end
|
| Line 3114... |
Line 3120... |
pc[`LOBYTE] <= dat;
|
pc[`LOBYTE] <= dat;
|
radr <= radr + 2'd1;
|
radr <= radr + 2'd1;
|
// If loading from the vector table in bank zero, force pc[23:16]=0
|
// If loading from the vector table in bank zero, force pc[23:16]=0
|
if (radr[`BYTE3]=={BPB{1'b0}} && radr[`BYTE2]=={BPB{1'b1}} && radr[7:4]==4'hF)
|
if (radr[`BYTE3]=={BPB{1'b0}} && radr[`BYTE2]=={BPB{1'b1}} && radr[7:4]==4'hF)
|
pc[`BYTE3] <= {BPB{1'b0}};
|
pc[`BYTE3] <= {BPB{1'b0}};
|
if (isRTI|isRTS|isPULS) begin
|
if (isRTI|isRTS|isRTF|isPULS) begin
|
$display("loadded PCL=%h", dat);
|
$display("loadded PCL=%h", dat);
|
ssp <= ssp + 2'd1;
|
ssp <= ssp + 2'd1;
|
end
|
end
|
else if (isPULU)
|
else if (isPULU)
|
usp <= usp + 2'd1;
|
usp <= usp + 2'd1;
|
| Line 3126... |
Line 3132... |
end
|
end
|
`LW_PCH: begin
|
`LW_PCH: begin
|
pc[`HIBYTE] <= dat;
|
pc[`HIBYTE] <= dat;
|
load_what <= `LW_PCL;
|
load_what <= `LW_PCL;
|
radr <= radr + 2'd1;
|
radr <= radr + 2'd1;
|
if (isRTI|isRTS|isPULS) begin
|
if (isRTI|isRTS|isRTF|isPULS) begin
|
$display("loadded PCH=%h", dat);
|
$display("loadded PCH=%h", dat);
|
ssp <= ssp + 2'd1;
|
ssp <= ssp + 2'd1;
|
end
|
end
|
else if (isPULU)
|
else if (isPULU)
|
usp <= usp + 2'd1;
|
usp <= usp + 2'd1;
|
