Subversion Repositories rf6809

                    i15,i14,i13,i12,i11,i10,i9,i8,i7,i6,i5,i4,i3,i2,i1,nmii};

                    i15,i14,i13,i12,i11,i10,i9,i8,i7,i6,i5,i4,i3,i2,i1,nmii};

reg [31:0] ib;

reg [31:0] ib;

reg [31:0] iedge;

reg [31:0] iedge;

reg [31:0] rste;

reg [31:0] rste;

reg [31:0] es;

reg [31:0] es;

reg [3:0] irq [0:31];

reg [3:0] irq [0:31];

reg [BPB:0] cause [0:31];

reg [BPB:0] cause [0:31];

reg [5:0] server [0:31];

reg [5:0] server [0:31];

integer n;

integer n;

                8'd6:   dat_o <= ie[15: 8];

                8'd6:   dat_o <= ie[15: 8];

                8'd7:   dat_o <= ie[ 7: 0];

                8'd7:   dat_o <= ie[ 7: 0];

                8'b1?????00: dat_o <= cause[adr_i[6:2]];

                8'b1?????00: dat_o <= cause[adr_i[6:2]];

                8'b1?????01: dat_o <= {es[adr_i[6:2]],ie[adr_i[6:2]],2'b0,irq[adr_i[6:2]]};

                8'b1?????01: dat_o <= {es[adr_i[6:2]],ie[adr_i[6:2]],2'b0,irq[adr_i[6:2]]};

                8'b1?????10:    dat_o <= {2'b0,server[adr_i[6:2]]};

                8'b1?????10:    dat_o <= {2'b0,server[adr_i[6:2]]};

                default:        dat_o <= 12'h00;

                default:        dat_o <= 12'h00;

                endcase

                endcase

        else

        else

                dat_o <= 12'h00;

                dat_o <= 12'h00;

end

end

// irq requests are latched on every rising clock edge to prevent

// irq requests are latched on every rising clock edge to prevent

// misreads

// misreads

// nmi is not encoded

// nmi is not encoded

always @(posedge clk)

always @(posedge clk)

        irqenc <= 5'd0;

        irqenc <= 5'd0;

                if ((es[n] ? iedge[n] : i[n])) irqenc <= n;

                if ((es[n] ? iedge[n] : i[n])) irqenc <= n;

end

end

endmodule

endmodule