| Line 7... |
Line 7... |
--
|
--
|
-- Description
|
-- Description
|
-- Contains automatic test code to verify a RioWbBridge implementation.
|
-- Contains automatic test code to verify a RioWbBridge implementation.
|
--
|
--
|
-- To Do:
|
-- To Do:
|
-- -
|
-- REMARK: Move the testport package and entities to a seperate file.
|
--
|
--
|
-- Author(s):
|
-- Author(s):
|
-- - Magnus Rosenius, magro732@opencores.org
|
-- - Magnus Rosenius, magro732@opencores.org
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--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
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| Line 40... |
Line 40... |
-- from http://www.opencores.org/lgpl.shtml
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-- from http://www.opencores.org/lgpl.shtml
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--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
|
|
-- REMARK: Move the testport package and entities to a seperate file.
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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| Line 557... |
Line 556... |
wait until clk = '1' or messageWrite_i = '1';
|
wait until clk = '1' or messageWrite_i = '1';
|
|
|
if (clk'event) then
|
if (clk'event) then
|
if (cyc_i = '1') then
|
if (cyc_i = '1') then
|
if (front /= back) then
|
if (front /= back) then
|
if (cyclePosition < queue(back).length) then
|
if (stb_i = '1') then
|
|
if (latencyCounter <= queue(back).latency) then
|
TestCompare(stb_i, '1', "stb_i");
|
TestCompare(stb_i, '1', "stb_i");
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if (queue(back).writeAccess) then
|
if (queue(back).writeAccess) then
|
TestCompare(we_i, '1', "we_i");
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TestCompare(we_i, '1', "we_i");
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else
|
else
|
TestCompare(we_i, '0', "we_i");
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TestCompare(we_i, '0', "we_i");
|
end if;
|
end if;
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-- REMARK: Add this...
|
TestCompare(adr_i, std_logic_vector(unsigned(queue(back).address)+cyclePosition), "adr_i");
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--TestCompare(adr_i, std_logic_vector(unsigned(queue(back).address)+cyclePosition), "adr_i");
|
|
TestCompare(sel_i, queue(back).byteSelect, "sel_i");
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TestCompare(sel_i, queue(back).byteSelect, "sel_i");
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if (queue(back).writeAccess) then
|
if (queue(back).writeAccess) then
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TestCompare(dat_i, queue(back).data(cyclePosition), "dat_i");
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TestCompare(dat_i, queue(back).data(cyclePosition), "dat_i");
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end if;
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end if;
|
|
end if;
|
|
|
if (latencyCounter = queue(back).latency) then
|
if (latencyCounter < queue(back).latency) then
|
dat_o <= queue(back).data(cyclePosition);
|
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ack_o <= '1';
|
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latencyCounter := 0;
|
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cyclePosition := cyclePosition + 1;
|
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else
|
|
dat_o <= (others=>'U');
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dat_o <= (others=>'U');
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ack_o <= '0';
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ack_o <= '0';
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latencyCounter := latencyCounter + 1;
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latencyCounter := latencyCounter + 1;
|
|
elsif (latencyCounter = queue(back).latency) then
|
|
if (queue(back).writeAccess) then
|
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dat_o <= (others=>'U');
|
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else
|
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dat_o <= queue(back).data(cyclePosition);
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end if;
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end if;
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ack_o <= '1';
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latencyCounter := latencyCounter + 1;
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else
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else
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back := QueueIndexInc(back);
|
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cyclePosition := 0;
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latencyCounter := 0;
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dat_o <= (others=>'U');
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dat_o <= (others=>'U');
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ack_o <= '0';
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ack_o <= '0';
|
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latencyCounter := 0;
|
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cyclePosition := cyclePosition + 1;
|
|
|
|
if (cyclePosition = queue(back).length) then
|
|
back := QueueIndexInc(back);
|
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cyclePosition := 0;
|
|
end if;
|
|
end if;
|
end if;
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end if;
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else
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else
|
TestError("Unexpected access.");
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TestError("Unexpected access.");
|
end if;
|
end if;
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else
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else
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| Line 910... |
Line 917... |
return "11111111";
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return "11111111";
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end case;
|
end case;
|
end function;
|
end function;
|
|
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
--
|
-- Local variables.
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
variable seed1 : positive := 1;
|
variable seed1 : positive := 1;
|
variable seed2: positive := 1;
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variable seed2: positive := 1;
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|
|
variable rdsize : std_logic_vector(3 downto 0);
|
variable rdsize : std_logic_vector(3 downto 0);
|
|
variable wrsize : std_logic_vector(3 downto 0);
|
variable wdptr : std_logic;
|
variable wdptr : std_logic;
|
|
variable maintData : DoubleWordArray(0 to 7);
|
variable ioData : DoubleWordArray(0 to 31);
|
variable ioData : DoubleWordArray(0 to 31);
|
variable frame : RioFrame;
|
variable frame : RioFrame;
|
|
|
begin
|
begin
|
areset_n <= '0';
|
areset_n <= '0';
|
| Line 952... |
Line 961... |
PrintS("-----------------------------------------------------------------");
|
PrintS("-----------------------------------------------------------------");
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
PrintR("TG_RioWbBridge-TC1-Step1");
|
PrintR("TG_RioWbBridge-TC1-Step1");
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
|
|
|
InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
|
|
tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,
|
|
sourceId=>x"dead", destId=>x"beef",
|
|
payload=>RioMaintenance(transaction=>"0000",
|
|
size=>"1000",
|
|
tid=>x"aa",
|
|
hopCount=>x"ff",
|
|
configOffset=>"000000000000000000000",
|
|
wdptr=>'0',
|
|
dataLength=>0,
|
|
data=>maintData)));
|
|
|
|
maintData(0) := x"deadbeef00000000";
|
|
OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
|
|
tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,
|
|
sourceId=>x"beef", destId=>x"dead",
|
|
payload=>RioMaintenance(transaction=>"0010",
|
|
size=>"0000",
|
|
tid=>x"aa",
|
|
hopCount=>x"ff",
|
|
configOffset=>"000000000000000000000",
|
|
wdptr=>'0',
|
|
dataLength=>1,
|
|
data=>maintData)));
|
|
|
|
TestWait(inboundEmpty, '1', "inbound frame");
|
|
TestWait(outboundEmpty, '1', "outbound frame");
|
|
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
PrintS("-----------------------------------------------------------------");
|
PrintS("-----------------------------------------------------------------");
|
PrintS("TG_RioWbBridge-TC2");
|
PrintS("TG_RioWbBridge-TC2");
|
PrintS("Description: Test request class packets.");
|
PrintS("Description: Test request class packets.");
|
PrintS("Requirement: XXXXX");
|
PrintS("Requirement: XXXXX");
|
PrintS("-----------------------------------------------------------------");
|
PrintS("-----------------------------------------------------------------");
|
PrintS("Step 1:");
|
PrintS("Step 1:");
|
PrintS("Action: Send maintenance read request for one word on even offset.");
|
PrintS("Action: Send request class NREAD packets for all sizes.");
|
PrintS("Result: Check the accesses on the external configuration port.");
|
PrintS("Result: The Wishbone access should match the inbound packet.");
|
PrintS("-----------------------------------------------------------------");
|
PrintS("-----------------------------------------------------------------");
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
PrintR("TG_RioWbBridge-TC2-Step1");
|
PrintR("TG_RioWbBridge-TC2-Step1");
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
-- REMARK: Change the address also...
|
-- REMARK: Change the address and tid also...
|
for i in 0 to 15 loop
|
for i in 0 to 15 loop
|
for j in 0 to 1 loop
|
for j in 0 to 1 loop
|
rdsize := std_logic_vector(to_unsigned(i, 4));
|
rdsize := std_logic_vector(to_unsigned(i, 4));
|
if (j = 0) then
|
if (j = 0) then
|
wdptr := '0';
|
wdptr := '0';
|
| Line 1002... |
Line 1039... |
ioData);
|
ioData);
|
|
|
TestWait(inboundEmpty, '1', "inbound frame");
|
TestWait(inboundEmpty, '1', "inbound frame");
|
TestWait(outboundEmpty, '1', "outbound frame");
|
TestWait(outboundEmpty, '1', "outbound frame");
|
TestWait(wbMessageEmpty, '1', "wishbone access");
|
TestWait(wbMessageEmpty, '1', "wishbone access");
|
|
end loop;
|
|
end loop;
|
|
|
|
---------------------------------------------------------------------------
|
|
PrintS("-----------------------------------------------------------------");
|
|
PrintS("TG_RioWbBridge-TC3");
|
|
PrintS("Description: Test write class packets.");
|
|
PrintS("Requirement: XXXXX");
|
|
PrintS("-----------------------------------------------------------------");
|
|
PrintS("Step 1:");
|
|
PrintS("Action: Send write class NWRITER packets for all sizes.");
|
|
PrintS("Result: The Wishbone access should match the inbound packet and a ");
|
|
PrintS(" response should be sent.");
|
|
PrintS("-----------------------------------------------------------------");
|
|
---------------------------------------------------------------------------
|
|
PrintR("TG_RioWbBridge-TC3-Step1");
|
|
---------------------------------------------------------------------------
|
|
-- REMARK: Change the address and tid also...
|
|
for i in 0 to 15 loop
|
|
for j in 0 to 1 loop
|
|
wrsize := std_logic_vector(to_unsigned(i, 4));
|
|
if (j = 0) then
|
|
wdptr := '0';
|
|
else
|
|
wdptr:= '1';
|
|
end if;
|
|
|
|
CreateRandomPayload(ioData, seed1, seed2);
|
|
|
|
InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
|
|
tt=>"01", ftype=>FTYPE_WRITE_CLASS,
|
|
sourceId=>x"dead", destId=>x"beef",
|
|
payload=>RioNwriteR(wrsize=>wrsize,
|
|
tid=>x"aa",
|
|
address=>"00000000000000000000000000000",
|
|
wdptr=>wdptr,
|
|
xamsbs=>"00",
|
|
dataLength=>getReadSize(wrsize, wdptr),
|
|
data=>ioData)));
|
|
|
|
OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
|
|
tt=>"01", ftype=>FTYPE_RESPONSE_CLASS,
|
|
sourceId=>x"beef", destId=>x"dead",
|
|
payload=>RioResponse(status=>"0000",
|
|
tid=>x"aa",
|
|
dataLength=>0,
|
|
data=>ioData)));
|
|
|
|
SetSlaveAccess(true, "0000000000000000000000000000000",
|
|
getReadMask(wrsize, wdptr),
|
|
getReadSize(wrsize, wdptr),
|
|
ioData);
|
|
|
|
TestWait(inboundEmpty, '1', "inbound frame");
|
|
TestWait(outboundEmpty, '1', "outbound frame");
|
|
TestWait(wbMessageEmpty, '1', "wishbone access");
|
|
end loop;
|
|
end loop;
|
|
|
|
---------------------------------------------------------------------------
|
|
PrintS("-----------------------------------------------------------------");
|
|
PrintS("Step 2:");
|
|
PrintS("Action: Send write class NWRITE packets for all sizes.");
|
|
PrintS("Result: The Wishbone access should match the inbound packet.");
|
|
PrintS("-----------------------------------------------------------------");
|
|
---------------------------------------------------------------------------
|
|
PrintR("TG_RioWbBridge-TC3-Step2");
|
|
---------------------------------------------------------------------------
|
|
-- REMARK: Change the address and tid also...
|
|
for i in 0 to 15 loop
|
|
for j in 0 to 1 loop
|
|
wrsize := std_logic_vector(to_unsigned(i, 4));
|
|
if (j = 0) then
|
|
wdptr := '0';
|
|
else
|
|
wdptr:= '1';
|
|
end if;
|
|
|
|
CreateRandomPayload(ioData, seed1, seed2);
|
|
|
|
InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
|
|
tt=>"01", ftype=>FTYPE_WRITE_CLASS,
|
|
sourceId=>x"dead", destId=>x"beef",
|
|
payload=>RioNwrite(wrsize=>wrsize,
|
|
address=>"00000000000000000000000000000",
|
|
wdptr=>wdptr,
|
|
xamsbs=>"00",
|
|
dataLength=>getReadSize(wrsize, wdptr),
|
|
data=>ioData)));
|
|
|
|
SetSlaveAccess(true, "0000000000000000000000000000000",
|
|
getReadMask(wrsize, wdptr),
|
|
getReadSize(wrsize, wdptr),
|
|
ioData);
|
|
|
|
TestWait(inboundEmpty, '1', "inbound frame");
|
|
TestWait(outboundEmpty, '1', "outbound frame");
|
|
TestWait(wbMessageEmpty, '1', "wishbone access");
|
end loop;
|
end loop;
|
end loop;
|
end loop;
|
|
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
-- Test completed.
|
-- Test completed.
|
