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[/] [rio/] [branches/] [2.0.0-development/] [bench/] [vhdl/] [TestRioWbBridge.vhd] - Diff between revs 48 and 51

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Rev 48 Rev 51
Line 370... Line 370...
    areset_n <= '1';
    areset_n <= '1';
    wait until clk'event and clk = '1';
    wait until clk'event and clk = '1';
    wait until clk'event and clk = '1';
    wait until clk'event and clk = '1';
 
 
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    TestSpec("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge");
    TestSpec("TG_RioWbBridge");
    PrintS("-----------------------------------------------------------------");
    TestSpec("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge-TC1");
    TestSpec("TG_RioWbBridge-TC1");
    PrintS("Description: Test maintenance requests.");
    TestSpec("Description: Test maintenance requests.");
    PrintS("Requirement: XXXXX");
    TestSpec("Requirement: XXXXX");
    PrintS("-----------------------------------------------------------------");
    TestSpec("-----------------------------------------------------------------");
    PrintS("Step 1:");
    TestSpec("Step 1:");
    PrintS("Action: Send maintenance read request for one word on even offset.");
    TestSpec("Action: Send maintenance read request for one word on even offset.");
    PrintS("Result: Check the accesses on the external configuration port.");
    TestSpec("Result: Check the accesses on the external configuration port.");
    PrintS("-----------------------------------------------------------------");
    TestSpec("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC1-Step1");
    TestCaseStart("TG_RioWbBridge-TC1-Step1");
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
 
 
    InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
    InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,
                                tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,
                                sourceId=>x"dead", destId=>x"beef",
                                sourceId=>x"dead", destId=>x"beef",
Line 414... Line 414...
 
 
    TestWait(inboundEmpty, '1', "inbound frame");
    TestWait(inboundEmpty, '1', "inbound frame");
    TestWait(outboundEmpty, '1', "outbound frame");
    TestWait(outboundEmpty, '1', "outbound frame");
 
 
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    TestSpec("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge-TC2");
    TestSpec("TG_RioWbBridge-TC2");
    PrintS("Description: Test request class packets.");
    TestSpec("Description: Test request class packets.");
    PrintS("Requirement: XXXXX");
    TestSpec("Requirement: XXXXX");
    PrintS("-----------------------------------------------------------------");
    TestSpec("-----------------------------------------------------------------");
    PrintS("Step 1:");
    TestSpec("Step 1:");
    PrintS("Action: Send request class NREAD packets for all sizes.");
    TestSpec("Action: Send request class NREAD packets for all sizes.");
    PrintS("Result: The Wishbone access should match the inbound packet.");
    TestSpec("Result: The Wishbone access should match the inbound packet.");
    PrintS("-----------------------------------------------------------------");
    TestSpec("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC2-Step1");
    TestCaseStart("TG_RioWbBridge-TC2-Step1");
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    -- REMARK: Change the address and tid also...
    -- REMARK: Change the address and tid also...
    for i in 0 to 15 loop
    for i in 0 to 15 loop
      for j in 0 to 1 loop
      for j in 0 to 1 loop
        rdsize := std_logic_vector(to_unsigned(i, 4));
        rdsize := std_logic_vector(to_unsigned(i, 4));
Line 436... Line 436...
          wdptr := '0';
          wdptr := '0';
        else
        else
          wdptr := '1';
          wdptr := '1';
        end if;
        end if;
 
 
        ioData(0) := x"0001020304050607";
        CreateRandomPayload(ioData, seed1, seed2);
        ioData(1) := x"08090a0b0c0d0e0f";
 
        ioData(2) := x"1011121314151617";
 
        ioData(3) := x"18191a1b1c1d1e1f";
 
        ioData(4) := x"2021222324252627";
 
        ioData(5) := x"28292a2b2c2d2e2f";
 
        ioData(6) := x"3031323334353637";
 
        ioData(7) := x"38393a3b3c3d3e3f";
 
        ioData(8) := x"4041424344454647";
 
        ioData(9) := x"48494a4b4c4d4e4f";
 
        ioData(10) := x"5051525354555657";
 
        ioData(11) := x"58595a5b5c5d5e5f";
 
 
 
        InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
        InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                    tt=>"01", ftype=>FTYPE_REQUEST_CLASS,
                                    tt=>"01", ftype=>FTYPE_REQUEST_CLASS,
                                    sourceId=>x"dead", destId=>x"beef",
                                    sourceId=>x"dead", destId=>x"beef",
                                    payload=>RioNread(rdsize=>rdsize,
                                    payload=>RioNread(rdsize=>rdsize,
Line 478... Line 467...
        TestWait(wbMessageEmpty, '1', "wishbone access");
        TestWait(wbMessageEmpty, '1', "wishbone access");
      end loop;
      end loop;
    end loop;
    end loop;
 
 
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    TestSpec("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge-TC3");
    TestSpec("TG_RioWbBridge-TC3");
    PrintS("Description: Test write class packets.");
    TestSpec("Description: Test write class packets.");
    PrintS("Requirement: XXXXX");
    TestSpec("Requirement: XXXXX");
    PrintS("-----------------------------------------------------------------");
    TestSpec("-----------------------------------------------------------------");
    PrintS("Step 1:");
    TestSpec("Step 1:");
    PrintS("Action: Send write class NWRITER packets for all sizes.");
    TestSpec("Action: Send write class NWRITER packets for all sizes.");
    PrintS("Result: The Wishbone access should match the inbound packet and a ");
    TestSpec("Result: The Wishbone access should match the inbound packet and a ");
    PrintS("        response should be sent.");
    TestSpec("        response should be sent.");
    PrintS("-----------------------------------------------------------------");
    TestSpec("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC3-Step1");
    TestCaseStart("TG_RioWbBridge-TC3-Step1");
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    -- REMARK: Change the address and tid also...
    -- REMARK: Change the address and tid also...
    -- REMARK: Not really all sizes, add sizes in between the fixed as well.
    -- REMARK: Not really all sizes, add sizes in between the fixed as well.
    for i in 0 to 15 loop
    for i in 0 to 15 loop
      for j in 0 to 1 loop
      for j in 0 to 1 loop
Line 535... Line 524...
        TestWait(wbMessageEmpty, '1', "wishbone access");
        TestWait(wbMessageEmpty, '1', "wishbone access");
      end loop;
      end loop;
    end loop;
    end loop;
 
 
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    TestSpec("-----------------------------------------------------------------");
    PrintS("Step 2:");
    TestSpec("Step 2:");
    PrintS("Action: Send write class NWRITE packets for all sizes.");
    TestSpec("Action: Send write class NWRITE packets for all sizes.");
    PrintS("Result: The Wishbone access should match the inbound packet.");
    TestSpec("Result: The Wishbone access should match the inbound packet.");
    PrintS("-----------------------------------------------------------------");
    TestSpec("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC3-Step2");
    TestCaseStart("TG_RioWbBridge-TC3-Step2");
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    -- REMARK: Change the address and tid also...
    -- REMARK: Change the address and tid also...
    for i in 0 to 15 loop
    for i in 0 to 15 loop
      for j in 0 to 1 loop
      for j in 0 to 1 loop
        wrsize := std_logic_vector(to_unsigned(i, 4));
        wrsize := std_logic_vector(to_unsigned(i, 4));

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