| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- RioLogicalCommon.
|
-- RioLogicalCommon.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Ingress:
|
-- Ingress:
|
-- * Removes in-the-middle-CRC.
|
-- * Removes in-the-middle and trailing CRC.
|
-- * Forwards packets to logical-layer handlers depending on ftype and
|
-- * Forwards packets to logical-layer handlers depending on ftype and
|
-- transaction (output as address).
|
-- transaction (output as address).
|
-- * Outputs header and deviceIDs in seperate accesses to facilitate 8- and
|
-- * Outputs header and deviceIDs in seperate accesses to facilitate 8- and
|
-- 16-bit deviceAddress support. All fields are right-justified.
|
-- 16-bit deviceAddress support. All fields are right-justified.
|
-- Egress:
|
-- Egress:
|
-- * Adds CRC.
|
-- * Adds in-the-middle and trailing CRC.
|
-- * Receives packets from logical-layer handlers.
|
-- * Receives packets from logical-layer handlers.
|
|
-- * Receives header and deviceIDs in seperate accesses to facilitate 8- and
|
|
-- 16-bit deviceAddress support. All fields are right-justified.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- REMARK: Egress; Places packets in different queues depending on the packet priority?
|
-- REMARK: Egress; Places packets in different queues depending on the packet priority?
|
-- REMARK: Use inputOutput/message/maintenance/gsm/...-strobes instead?
|
-- REMARK: Use inputOutput/message/maintenance/gsm/...-strobes instead?
|
-- REMARK: If the deviceId:s are removed, it will work for both 8/16-bit deviceIds.
|
-- REMARK: If the deviceId:s are removed, it will work for both 8/16-bit deviceIds.
|
-- case (ftype) is
|
-- case (ftype) is
|
| Line 81... |
Line 83... |
-- shifter: 16 (48 empty)
|
-- shifter: 16 (48 empty)
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- RioLogicalCommonIngress.
|
-- RioLogicalCommonIngress.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
-- REMARK: Check the destination address to see if it matches the one configured???
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
use work.rio_common.all;
|
use work.rio_common.all;
|
|
|
| Line 102... |
Line 105... |
readContentEnd_i : in std_logic;
|
readContentEnd_i : in std_logic;
|
readContentData_i : in std_logic_vector(31 downto 0);
|
readContentData_i : in std_logic_vector(31 downto 0);
|
|
|
masterCyc_o : out std_logic;
|
masterCyc_o : out std_logic;
|
masterStb_o : out std_logic;
|
masterStb_o : out std_logic;
|
masterAddress_o : out std_logic_vector(7 downto 0);
|
masterAdr_o : out std_logic_vector(7 downto 0);
|
masterData_o : out std_logic_vector(31 downto 0);
|
masterSel_o : out std_logic_vector(3 downto 0);
|
|
masterDat_o : out std_logic_vector(31 downto 0);
|
masterAck_i : in std_logic);
|
masterAck_i : in std_logic);
|
end entity;
|
end entity;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
| Line 173... |
Line 177... |
when SEND_HEADER =>
|
when SEND_HEADER =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
masterStb_o <= '1';
|
masterStb_o <= '1';
|
masterAddress_o <= ftype & transaction;
|
masterAdr_o <= ftype & transaction;
|
masterData_o <= x"0000" & packetContent(63 downto 48);
|
masterSel_o <= x"0011";
|
|
masterDat_o <= x"0000" & packetContent(63 downto 48);
|
packetContent <= packetContent(47 downto 0) & x"0000";
|
packetContent <= packetContent(47 downto 0) & x"0000";
|
|
|
state <= SEND_DESTINATION;
|
state <= SEND_DESTINATION;
|
|
|
when SEND_DESTINATION =>
|
when SEND_DESTINATION =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (masterAck_i = '1') then
|
if (masterAck_i = '1') then
|
if (tt = "00") then
|
if (tt = "00") then
|
masterData_o <= x"000000" & packetContent(63 downto 56);
|
masterSel_o <= x"0001";
|
|
masterDat_o <= x"000000" & packetContent(63 downto 56);
|
packetContent <= packetContent(55 downto 0) & x"00";
|
packetContent <= packetContent(55 downto 0) & x"00";
|
elsif (tt = "01") then
|
elsif (tt = "01") then
|
masterData_o <= x"0000" & packetContent(63 downto 48);
|
masterSel_o <= x"0011";
|
|
masterDat_o <= x"0000" & packetContent(63 downto 48);
|
packetContent <= packetContent(31 downto 0) & readContentData_i;
|
packetContent <= packetContent(31 downto 0) & readContentData_i;
|
readContent_o <= '1';
|
readContent_o <= '1';
|
end if;
|
end if;
|
|
|
state <= SEND_SOURCE;
|
state <= SEND_SOURCE;
|
| Line 202... |
Line 209... |
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (masterAck_i = '1') then
|
if (masterAck_i = '1') then
|
if (tt = "00") then
|
if (tt = "00") then
|
masterData_o <= x"000000" & packetContent(63 downto 56);
|
masterSel_o <= x"0001";
|
|
masterDat_o <= x"000000" & packetContent(63 downto 56);
|
packetContent <= packetContent(55 downto 0) & x"00";
|
packetContent <= packetContent(55 downto 0) & x"00";
|
elsif (tt = "01") then
|
elsif (tt = "01") then
|
masterData_o <= x"0000" & packetContent(63 downto 48);
|
masterSel_o <= x"0011";
|
|
masterDat_o <= x"0000" & packetContent(63 downto 48);
|
packetContent <= packetContent(47 downto 0) & x"0000";
|
packetContent <= packetContent(47 downto 0) & x"0000";
|
end if;
|
end if;
|
|
|
state <= FORWARD;
|
state <= FORWARD;
|
end if;
|
end if;
|
| Line 217... |
Line 226... |
when FORWARD =>
|
when FORWARD =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (masterAck_i = '1') then
|
if (masterAck_i = '1') then
|
masterData_o <= packetContent(63 downto 32);
|
masterSel_o <= x"1111";
|
|
masterDat_o <= packetContent(63 downto 32);
|
|
|
packetPosition <= packetPosition + 1;
|
packetPosition <= packetPosition + 1;
|
|
|
-- REMARK: Rewrite depending on tt-field to compensate for
|
-- REMARK: Rewrite depending on tt-field to compensate for
|
-- different number of valid bits in the shifter...
|
-- different number of valid bits in the shifter...
|
| Line 246... |
Line 256... |
|
|
when FORWARD_LAST =>
|
when FORWARD_LAST =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
|
-- REMARK: The last always contain the CRC?
|
if (masterAck_i = '1') then
|
if (masterAck_i = '1') then
|
masterData_o <= packetContent(63 downto 32);
|
masterSel_o <= x"1111";
|
|
masterDat_o <= packetContent(63 downto 32);
|
state <= END_PACKET;
|
state <= END_PACKET;
|
end if;
|
end if;
|
|
|
when END_PACKET =>
|
when END_PACKET =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
| Line 337... |
Line 349... |
case state is
|
case state is
|
when IDLE =>
|
when IDLE =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
|
packetPosition <= 0;
|
if (writeFrameFull_i = '0') then
|
if (writeFrameFull_i = '0') then
|
state <= HEADER_GET;
|
state <= HEADER_GET;
|
packetPosition <= 0;
|
|
crc16Current <= x"ffff";
|
crc16Current <= x"ffff";
|
end if;
|
end if;
|
|
|
when GET_HEADER =>
|
when GET_HEADER =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
| Line 359... |
Line 371... |
tt <= slaveData_i(13 downto 12);
|
tt <= slaveData_i(13 downto 12);
|
elsif (slaveSelect_i = "0011") then
|
elsif (slaveSelect_i = "0011") then
|
header <= slaveData_i(15 downto 0);
|
header <= slaveData_i(15 downto 0);
|
tt <= slaveData_i(5 downto 4);
|
tt <= slaveData_i(5 downto 4);
|
else
|
else
|
-- Not supported.
|
-- REMARK: Not supported.
|
end if;
|
end if;
|
|
|
slaveAck_o <= '1';
|
slaveAck_o <= '1';
|
|
|
state <= HEADER_ACK;
|
state <= HEADER_ACK;
|
| Line 606... |
Line 618... |
d_i=>writeContentData(31 downto 16), crc_i=>crc16Current, crc_o=>crc16Temp);
|
d_i=>writeContentData(31 downto 16), crc_i=>crc16Current, crc_o=>crc16Temp);
|
Crc16Low: Crc16CITT
|
Crc16Low: Crc16CITT
|
port map(
|
port map(
|
d_i=>writeContentData(15 downto 0), crc_i=>crc16Temp, crc_o=>crc16Next);
|
d_i=>writeContentData(15 downto 0), crc_i=>crc16Temp, crc_o=>crc16Next);
|
|
|
|
|
end architecture;
|
end architecture;
|
|
|
|
|
|
|
|
|
| Line 623... |
Line 634... |
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
use work.rio_common.all;
|
use work.rio_common.all;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Entity for RioLogicalMaintenanceRequest.
|
-- Entity for RioLogicalMaintenanceRequest.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
entity RioLogicalMaintenanceRequest is
|
entity RioLogicalMaintenanceRequest is
|
generic(
|
generic(
|
| Line 639... |
Line 651... |
DEFAULT_BASE_DEVICE_ID : std_logic_vector(15 downto 0) := x"ffff");
|
DEFAULT_BASE_DEVICE_ID : std_logic_vector(15 downto 0) := x"ffff");
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
areset_n : in std_logic;
|
areset_n : in std_logic;
|
|
|
|
configStb_o : out std_logic;
|
|
configWe_o : out std_logic;
|
|
configAdr_o : out std_logic_vector(23 downto 0);
|
|
configDat_o : out std_logic_vector(63 downto 0);
|
|
configSel_o : out std_logic_vector(7 downto 0);
|
|
configDat_i : in std_logic_vector(63 downto 0);
|
|
configAck_i : in std_logic;
|
|
|
slaveCyc_i : in std_logic;
|
slaveCyc_i : in std_logic;
|
slaveStb_i : in std_logic;
|
slaveStb_i : in std_logic;
|
slaveAdr_i : in std_logic_vector(7 downto 0);
|
slaveAdr_i : in std_logic_vector(7 downto 0);
|
slaveDat_i : in std_logic_vector(31 downto 0);
|
slaveDat_i : in std_logic_vector(31 downto 0);
|
slaveAck_o : out std_logic;
|
slaveAck_o : out std_logic;
|
|
|
masterCyc_o : out std_logic;
|
masterCyc_o : out std_logic;
|
masterStb_o : out std_logic;
|
masterStb_o : out std_logic;
|
masterSel_o : out std_logic_vector(3 downto 0);
|
|
masterDat_o : out std_logic_vector(31 downto 0);
|
masterDat_o : out std_logic_vector(31 downto 0);
|
masterAck_i : in std_logic);
|
masterAck_i : in std_logic);
|
end entity;
|
end entity;
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
--
|
|
-------------------------------------------------------------------------------
|
architecture RioLogicalMaintenanceRequest of RioLogicalMaintenanceRequest is
|
architecture RioLogicalMaintenanceRequest of RioLogicalMaintenanceRequest is
|
|
component MemorySinglePort is
|
|
generic(
|
|
ADDRESS_WIDTH : natural := 1;
|
|
DATA_WIDTH : natural := 1);
|
|
port(
|
|
clk_i : in std_logic;
|
|
enable_i : in std_logic;
|
|
writeEnable_i : in std_logic;
|
|
address_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
|
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
|
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
|
end component;
|
|
|
begin
|
begin
|
|
|
slaveAck_o <= slaveAck;
|
slaveAck_o <= slaveAck;
|
MaintenanceRequest: process(clk, areset_n)
|
MaintenanceRequest: process(clk, areset_n)
|
begin
|
begin
|
if (areset_n = '0') then
|
if (areset_n = '0') then
|
|
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
if (slaveCyc_i = '0') then
|
case state is
|
packetIndex <= 0;
|
when WAIT_PACKET =>
|
elsif (slaveStb_i = '1') then
|
---------------------------------------------------------------------
|
|
--
|
|
---------------------------------------------------------------------
|
|
if (slaveCyc_i = '1') then
|
if (slaveAck = '0') then
|
if (slaveAck = '0') then
|
|
if (slaveStb_i = '1') then
|
if (slaveAddress_i = x"80") then
|
if (slaveAddress_i = x"80") then
|
-- Maintenance read request.
|
-- Maintenance read request.
|
case (packetIndex) is
|
case (packetIndex) is
|
when 0 =>
|
when 0 =>
|
-- x"0000" & ackid & vc & crf & prio & tt & ftype
|
-- x"0000" & ackid & vc & crf & prio & tt & ftype
|
|
header <= slaveDat_i(15 downto 0);
|
when 1 =>
|
when 1 =>
|
-- destId
|
-- destId
|
|
destId <= slaveDat_i;
|
when 2 =>
|
when 2 =>
|
-- srcId
|
-- srcId
|
|
srcId <= slaveDat_i;
|
when 3 =>
|
when 3 =>
|
-- transaction & rdsize & srcTID & hop & config_offset(20:13)
|
-- transaction & rdsize & srcTID & hop & config_offset(20:13)
|
|
size <= slaveDat_i(27 downto 24);
|
|
srcTid <= slaveDat_i(23 downto 16);
|
|
configOffset(20 downto 13) <= slaveDat_i(7 downto 0);
|
when 4 =>
|
when 4 =>
|
-- config_offset(12:0) & wdptr & rsrv & crc(15:0)
|
-- config_offset(12:0) & wdptr & rsrv & crc(15:0)
|
|
configOffset(12 downto 0) <= slaveDat_i(31 downto 16);
|
|
wdptr <= slaveDat_i(18);
|
|
maintReadComplete <= '1';
|
when others =>
|
when others =>
|
-- REMARK: Larger packets not supported.
|
-- There should be no more content in a maintenance read request.
|
|
-- Discard.
|
end case;
|
end case;
|
elsif (slaveAddress_i = x"81") then
|
elsif (slaveAddress_i = x"81") then
|
-- Maintenance write request.
|
-- Maintenance write request.
|
case (packetIndex) is
|
case (packetIndex) is
|
when 0 =>
|
when 0 =>
|
-- x"0000" & ackid & vc & crf & prio & tt & ftype
|
-- x"0000" & ackid & vc & crf & prio & tt & ftype
|
|
header <= slaveDat_i(15 downto 0);
|
when 1 =>
|
when 1 =>
|
-- destId
|
-- destId
|
|
destId <= slaveDat_i;
|
when 2 =>
|
when 2 =>
|
-- srcId
|
-- srcId
|
|
srcId <= slaveDat_i;
|
when 3 =>
|
when 3 =>
|
-- transaction & wrsize & srcTID & hop & config_offset(20:13)
|
-- transaction & wrsize & srcTID & hop & config_offset(20:13)
|
|
size <= slaveDat_i(27 downto 24);
|
|
srcTid <= slaveDat_i(23 downto 16);
|
|
configOffset(20 downto 13) <= slaveDat_i(7 downto 0);
|
when 4 =>
|
when 4 =>
|
-- config_offset(12:0) & wdptr & rsrv & double-word(63:48)
|
-- config_offset(12:0) & wdptr & rsrv & double-word(63:48)
|
when 5 =>
|
configOffset(12 downto 0) <= slaveDat_i(31 downto 16);
|
|
configData(63 downto 48) <= slaveData_i(15 downto 0);
|
|
wdptr <= slaveDat_i(18);
|
|
memoryEnable <= '1';
|
|
memoryAddress <= 0;
|
|
when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 =>
|
-- double-word(47:16)
|
-- double-word(47:16)
|
when 6 =>
|
configData(47 downto 16) <= slaveData_i;
|
-- double-word(15:0) & crc(15:0)
|
when 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 =>
|
|
-- double-word(15:0) & double-word(63:48)
|
|
memoryAddress <= memoryAddress + 1;
|
|
memoryWrite <= '1';
|
|
memoryDataIn <= configData(63 downto 16) & slaveData_i(31 downto 16);
|
|
configData(63 downto 48) <= slaveData_i(15 downto 0);
|
|
maintWriteComplete <= '1';
|
when others =>
|
when others =>
|
-- REMARK: Larger packets not supported.
|
-- There should be no more content in a maintenance read request.
|
|
-- Discard.
|
end case;
|
end case;
|
end if;
|
end if;
|
slaveAck <= '1';
|
slaveAck <= '1';
|
|
end if;
|
else
|
else
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
slaveAck <= '0';
|
slaveAck <= '0';
|
end if;
|
end if;
|
|
else
|
|
if (maintReadComplete = '1') then
|
|
state <= CONFIG_READ;
|
|
configIterator <= bytes;
|
|
memoryEnable <= '1';
|
|
memoryAddress <= 0;
|
end if;
|
end if;
|
|
if (maintWriteComplete = '1') then
|
|
state <= CONFIG_WRITE;
|
|
end if;
|
|
packetIndex <= 0;
|
|
maintReadComplete <= '0';
|
|
maintWriteComplete <= '0';
|
end if;
|
end if;
|
end process;
|
|
|
|
|
when CONFIG_READ =>
|
|
---------------------------------------------------------------------
|
|
--
|
|
---------------------------------------------------------------------
|
|
configStb_o <= '1';
|
|
configWe_o <= '0';
|
|
configAdr_o <= configOffset;
|
|
configSel_o <= byteLanes;
|
|
configIterator <= configIterator - 1;
|
|
configSpaceState <= CONFIG_READ_ACK;
|
|
|
|
when CONFIG_READ_ACK =>
|
|
---------------------------------------------------------------------
|
|
--
|
|
---------------------------------------------------------------------
|
|
if (configAck_i = '1') then
|
|
memoryAddress <= memoryAddress + 1;
|
|
memoryWrite <= '1';
|
|
memoryDataIn <= configSpaceDat_i;
|
|
|
|
if (configIterator /= 0) then
|
|
configAdr_o <= configAdr_o + 1;
|
|
state <= CONFIG_READ;
|
|
else
|
|
configStb_o <= '0';
|
|
packetIndex <= 0;
|
|
state <= CONFIG_READ_RESPONSE;
|
|
end if;
|
|
end if;
|
|
|
|
when CONFIG_READ_RESPONSE =>
|
|
---------------------------------------------------------------------
|
|
--
|
|
---------------------------------------------------------------------
|
|
masterCyc_o <= '1';
|
|
masterStb_o <= '1';
|
|
masterDat_o <= header;
|
|
packetIndex <= packetIndex + 1;
|
|
state <= CONFIG_READ_RESPONSE_ACK;
|
|
|
|
when CONFIG_READ_RESPONSE_ACK =>
|
|
---------------------------------------------------------------------
|
|
--
|
|
---------------------------------------------------------------------
|
|
if (masterAck_i = '1') then
|
|
masterCyc_o <= '1';
|
|
masterStb_o <= '1';
|
|
case (packetIndex) is
|
|
when 0 =>
|
|
-- x"0000" & ackid & vc & crf & prio & tt & ftype
|
|
masterDat_o <= header;
|
|
when 1 =>
|
|
-- destination is the source.
|
|
masterDat_o <= srcId;
|
|
when 2 =>
|
|
-- source is the destination.
|
|
masterDat_o <= destId;
|
|
when 3 =>
|
|
-- transaction & status & targetTID & hop & reserved(7:0)
|
|
masterDat_o <= "0010" & "0000" & srcTid & x"ff" & x"00";
|
|
when 4 =>
|
|
-- reserved(15:0) & double-word0(63:32)
|
|
masterDat_o <= x"0000" & memoryDataOut(63 downto 32);
|
|
when 5 =>
|
|
masterDat_o <= memoryDataOut(31 downto 0) & x"0000";
|
|
-- REMARK: Add more here to send the full response...
|
|
when others =>
|
|
state <= WAIT_PACKET;
|
|
end case;
|
|
packetIndex <= packetIndex + 1;
|
|
end if;
|
|
|
|
when CONFIG_WRITE =>
|
|
---------------------------------------------------------------------
|
|
--
|
|
---------------------------------------------------------------------
|
|
|
|
when others =>
|
|
|
|
end case;
|
|
end if;
|
|
end process;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- findInPayload
|
--
|
-- find out number of the bytes and first byte's position in the payload.
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
findInPayload: process(wdptr, size)
|
-- REMARK: Make this a common component?
|
|
-- REMARK: Change bytes to double-words?
|
|
process(wdptr, size)
|
begin
|
begin
|
case size is
|
case (wdptr & size) is
|
when "0000" =>
|
when "00000" =>
|
reserved <= '0';
|
bytes <= 1;
|
numberOfByte <= 1;
|
byteLanes <= "10000000";
|
if wdptr = '1' then
|
when "00001" =>
|
pos <= 4;
|
bytes <= 1;
|
else
|
byteLanes <= "01000000";
|
pos <= 0;
|
|
end if;
|
when "00010" =>
|
when "0001" =>
|
bytes <= 1;
|
reserved <= '0';
|
byteLanes <= "00100000";
|
numberOfByte <= 1;
|
when "00011" =>
|
if wdptr = '1' then
|
bytes <= 1;
|
pos <= 5;
|
byteLanes <= "00010000";
|
else
|
|
pos <= 1;
|
when "10000" =>
|
end if;
|
bytes <= 1;
|
when "0010" =>
|
byteLanes <= "00001000";
|
reserved <= '0';
|
when "10001" =>
|
numberOfByte <= 1;
|
bytes <= 1;
|
if wdptr = '1' then
|
byteLanes <= "00000100";
|
pos <= 6;
|
|
else
|
when "10010" =>
|
pos <= 2;
|
bytes <= 1;
|
end if;
|
byteLanes <= "00000010";
|
when "0011" =>
|
when "10011" =>
|
reserved <= '0';
|
bytes <= 1;
|
numberOfByte <= 1;
|
byteLanes <= "00000001";
|
if wdptr = '1' then
|
|
pos <= 7;
|
when "00100" =>
|
else
|
bytes <= 2;
|
pos <= 3;
|
byteLanes <= "11000000";
|
end if;
|
when "00101" =>
|
when "0100" =>
|
bytes <= 3;
|
reserved <= '0';
|
byteLanes <= "11100000";
|
numberOfByte <= 2;
|
|
if wdptr = '1' then
|
when "00110" =>
|
pos <= 4;
|
bytes <= 2;
|
else
|
byteLanes <= "00110000";
|
pos <= 0;
|
when "00111" =>
|
end if;
|
bytes <= 5;
|
when "0101" =>
|
byteLanes <= "11111000";
|
reserved <= '0';
|
|
numberOfByte <= 3;
|
when "10100" =>
|
if wdptr = '1' then
|
bytes <= 2;
|
pos <= 5;
|
byteLanes <= "00001100";
|
else
|
when "10101" =>
|
pos <= 0;
|
bytes <= 3;
|
end if;
|
byteLanes <= "00000111";
|
when "0110" =>
|
|
reserved <= '0';
|
when "10110" =>
|
numberOfByte <= 2;
|
bytes <= 2;
|
if wdptr = '1' then
|
byteLanes <= "00000011";
|
pos <= 6;
|
when "10111" =>
|
else
|
bytes <= 5;
|
pos <= 2;
|
byteLanes <= "00011111";
|
end if;
|
|
when "0111" =>
|
when "01000" =>
|
reserved <= '0';
|
bytes <= 4;
|
numberOfByte <= 5;
|
byteLanes <= "11110000";
|
if wdptr = '1' then
|
when "11000" =>
|
pos <= 3;
|
bytes <= 4;
|
else
|
byteLanes <= "00001111";
|
pos <= 0;
|
|
end if;
|
when "01001" =>
|
when "1000" =>
|
bytes <= 6;
|
reserved <= '0';
|
byteLanes <= "11111100";
|
numberOfByte <= 4;
|
when "11001" =>
|
if wdptr = '1' then
|
bytes <= 6;
|
pos <= 4;
|
byteLanes <= "00111111";
|
else
|
|
pos <= 0;
|
when "01010" =>
|
end if;
|
bytes <= 7;
|
when "1001" =>
|
byteLanes <= "11111110";
|
reserved <= '0';
|
when "11010" =>
|
numberOfByte <= 6;
|
bytes <= 7;
|
if wdptr = '1' then
|
byteLanes <= "01111111";
|
pos <= 2;
|
|
else
|
when "01011" =>
|
pos <= 0;
|
bytes <= 8;
|
end if;
|
byteLanes <= "11111111";
|
when "1010" =>
|
when "11011" =>
|
reserved <= '0';
|
bytes <= 16;
|
numberOfByte <= 7;
|
byteLanes <= "11111111";
|
if wdptr = '1' then
|
|
pos <= 1;
|
when "01100" =>
|
else
|
bytes <= 32;
|
pos <= 0;
|
byteLanes <= "11111111";
|
end if;
|
when "11100" =>
|
when "1011" =>
|
bytes <= 64;
|
reserved <= '0';
|
byteLanes <= "11111111";
|
if wdptr = '1' then
|
|
numberOfByte <= 16;
|
when "01101" =>
|
else
|
bytes <= 96;
|
numberOfByte <= 8;
|
byteLanes <= "11111111";
|
end if;
|
when "11101" =>
|
pos <= 0;
|
bytes <= 128;
|
when "1100" =>
|
byteLanes <= "11111111";
|
reserved <= '0';
|
|
if wdptr = '1' then
|
when "01110" =>
|
numberOfByte <= 64;
|
bytes <= 160;
|
else
|
byteLanes <= "11111111";
|
numberOfByte <= 32;
|
when "11110" =>
|
end if;
|
bytes <= 192;
|
pos <= 0;
|
byteLanes <= "11111111";
|
when "1101" =>
|
|
if wdptr = '1' then
|
when "01111" =>
|
reserved <= '0';
|
bytes <= 224;
|
numberOfByte <= 128;
|
byteLanes <= "11111111";
|
else
|
when "11111" =>
|
reserved <= '1';
|
bytes <= 256;
|
numberOfByte <= 96;
|
byteLanes <= "11111111";
|
end if;
|
|
pos <= 0;
|
end case;
|
when "1110" =>
|
end process;
|
if wdptr = '1' then
|
|
numberOfByte <= 192;
|
end architecture;
|
else
|
|
numberOfByte <= 160;
|
|
end if;
|
entity MaintenanceReadRequestInbound is
|
reserved <= '1';
|
port(
|
pos <= 0;
|
clk : in std_logic;
|
when "1111" =>
|
areset_n : in std_logic;
|
if wdptr = '1' then
|
|
reserved <= '0';
|
slaveCyc_i : in std_logic;
|
numberOfByte <= 256;
|
slaveStb_i : in std_logic;
|
|
slaveAdr_i : in std_logic_vector(7 downto 0);
|
|
slaveDat_i : in std_logic_vector(31 downto 0);
|
|
slaveAck_o : out std_logic;
|
|
|
|
header_o : out std_logic_vector(15 downto 0);
|
|
dstId_o : out std_logic_vector(31 downto 0);
|
|
srcId_o : out std_logic_vector(31 downto 0);
|
|
tid_o : out std_logic_vector(7 downto 0);
|
|
configOffset_o : out std_logic_vector(21 downto 0);
|
|
configLength_o : out std_logic_vector(3 downto 0);
|
|
configSelect_o : out std_logic_vector(7 downto 0);
|
|
ready_o : out std_logic;
|
|
done_i : in std_logic);
|
|
end entity;
|
|
|
|
|
|
architecture MaintenanceReadRequestInbound of MaintenanceReadRequestInbound is
|
|
|
|
begin
|
|
|
|
ready_o <= maintReadComplete;
|
|
slaveAck_o <= slaveAck;
|
|
MaintenanceReadRequest: process(clk, areset_n)
|
|
begin
|
|
if (areset_n = '0') then
|
|
|
|
elsif (clk'event and clk = '1') then
|
|
case state is
|
|
when WAIT_PACKET =>
|
|
---------------------------------------------------------------------
|
|
--
|
|
---------------------------------------------------------------------
|
|
if (slaveCyc_i = '1') then
|
|
if (slaveAck = '0') then
|
|
if (slaveStb_i = '1') then
|
|
if (slaveAddress_i = x"80") then
|
|
case (packetIndex) is
|
|
when 0 =>
|
|
-- x"0000" & ackid & vc & crf & prio & tt & ftype
|
|
header <= slaveDat_i(15 downto 0);
|
|
packetIndex <= packetIndex + 1;
|
|
when 1 =>
|
|
-- destid
|
|
destId <= slaveDat_i;
|
|
packetIndex <= packetIndex + 1;
|
|
when 2 =>
|
|
-- srcid
|
|
srcId <= slaveDat_i;
|
|
packetIndex <= packetIndex + 1;
|
|
when 3 =>
|
|
-- transaction & rdsize & srcTID & hop & config_offset(20:13)
|
|
size <= slaveDat_i(27 downto 24);
|
|
srcTid <= slaveDat_i(23 downto 16);
|
|
configOffset(20 downto 13) <= slaveDat_i(7 downto 0);
|
|
packetIndex <= packetIndex + 1;
|
|
when 4 =>
|
|
-- config_offset(12:0) & wdptr & rsrv & crc(15:0)
|
|
configOffset(12 downto 0) <= slaveDat_i(31 downto 16);
|
|
wdptr <= slaveDat_i(18);
|
|
packetIndex <= packetIndex + 1;
|
|
maintReadComplete <= '1';
|
|
when others =>
|
|
-- There should be no more content in a maintenance read request.
|
|
-- Discard.
|
|
end case;
|
|
end if;
|
|
slaveAck <= '1';
|
|
end if;
|
|
else
|
|
slaveAck <= '0';
|
|
end if;
|
else
|
else
|
reserved <= '1';
|
if (maintReadComplete = '1') then
|
numberOfByte <= 224;
|
state <= READY;
|
end if;
|
end if;
|
pos <= 0;
|
packetIndex <= 0;
|
|
end if;
|
|
|
|
when READY =>
|
|
---------------------------------------------------------------------
|
|
--
|
|
---------------------------------------------------------------------
|
|
if (done_i = '1') then
|
|
maintReadComplete <= '0';
|
|
state <= WAIT_PACKET;
|
|
end if;
|
|
|
when others =>
|
when others =>
|
reserved <= '1';
|
|
numberOfByte <= 0;
|
end case;
|
pos <= 0;
|
end if;
|
|
end process;
|
|
|
|
-----------------------------------------------------------------------------
|
|
--
|
|
-----------------------------------------------------------------------------
|
|
-- REMARK: Make this a common component?
|
|
-- REMARK: Change bytes to double-words?
|
|
process(wdptr, size)
|
|
begin
|
|
case (wdptr & size) is
|
|
when "00000" =>
|
|
bytes <= 1;
|
|
byteLanes <= "10000000";
|
|
when "00001" =>
|
|
bytes <= 1;
|
|
byteLanes <= "01000000";
|
|
|
|
when "00010" =>
|
|
bytes <= 1;
|
|
byteLanes <= "00100000";
|
|
when "00011" =>
|
|
bytes <= 1;
|
|
byteLanes <= "00010000";
|
|
|
|
when "10000" =>
|
|
bytes <= 1;
|
|
byteLanes <= "00001000";
|
|
when "10001" =>
|
|
bytes <= 1;
|
|
byteLanes <= "00000100";
|
|
|
|
when "10010" =>
|
|
bytes <= 1;
|
|
byteLanes <= "00000010";
|
|
when "10011" =>
|
|
bytes <= 1;
|
|
byteLanes <= "00000001";
|
|
|
|
when "00100" =>
|
|
bytes <= 2;
|
|
byteLanes <= "11000000";
|
|
when "00101" =>
|
|
bytes <= 3;
|
|
byteLanes <= "11100000";
|
|
|
|
when "00110" =>
|
|
bytes <= 2;
|
|
byteLanes <= "00110000";
|
|
when "00111" =>
|
|
bytes <= 5;
|
|
byteLanes <= "11111000";
|
|
|
|
when "10100" =>
|
|
bytes <= 2;
|
|
byteLanes <= "00001100";
|
|
when "10101" =>
|
|
bytes <= 3;
|
|
byteLanes <= "00000111";
|
|
|
|
when "10110" =>
|
|
bytes <= 2;
|
|
byteLanes <= "00000011";
|
|
when "10111" =>
|
|
bytes <= 5;
|
|
byteLanes <= "00011111";
|
|
|
|
when "01000" =>
|
|
bytes <= 4;
|
|
byteLanes <= "11110000";
|
|
when "11000" =>
|
|
bytes <= 4;
|
|
byteLanes <= "00001111";
|
|
|
|
when "01001" =>
|
|
bytes <= 6;
|
|
byteLanes <= "11111100";
|
|
when "11001" =>
|
|
bytes <= 6;
|
|
byteLanes <= "00111111";
|
|
|
|
when "01010" =>
|
|
bytes <= 7;
|
|
byteLanes <= "11111110";
|
|
when "11010" =>
|
|
bytes <= 7;
|
|
byteLanes <= "01111111";
|
|
|
|
when "01011" =>
|
|
bytes <= 8;
|
|
byteLanes <= "11111111";
|
|
when "11011" =>
|
|
bytes <= 16;
|
|
byteLanes <= "11111111";
|
|
|
|
when "01100" =>
|
|
bytes <= 32;
|
|
byteLanes <= "11111111";
|
|
when "11100" =>
|
|
bytes <= 64;
|
|
byteLanes <= "11111111";
|
|
|
|
when "01101" =>
|
|
bytes <= 96;
|
|
byteLanes <= "11111111";
|
|
when "11101" =>
|
|
bytes <= 128;
|
|
byteLanes <= "11111111";
|
|
|
|
when "01110" =>
|
|
bytes <= 160;
|
|
byteLanes <= "11111111";
|
|
when "11110" =>
|
|
bytes <= 192;
|
|
byteLanes <= "11111111";
|
|
|
|
when "01111" =>
|
|
bytes <= 224;
|
|
byteLanes <= "11111111";
|
|
when "11111" =>
|
|
bytes <= 256;
|
|
byteLanes <= "11111111";
|
|
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
end architecture;
|
end architecture;
|
|
|
No newline at end of file
|
No newline at end of file
|
