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[/] [rio/] [branches/] [2.0.0-development/] [rtl/] [vhdl/] [RioLogicalCommon.vhd] - Diff between revs 35 and 36

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Line 1... Line 1... 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
 
 
-- 
 
 
-- RapidIO IP Library Core
 
 
 
-- 
 
 
-- This file is part of the RapidIO IP library project
 
 
 
-- http://www.opencores.org/cores/rio/
 
 
 
-- 
 
 
-- Description
 
 
 
-- Contains a platform to build endpoints on.
 
 
 
-- 
 
 
-- To Do:
 
 
 
-- -
 
 
 
-- 
 
 
-- Author(s): 
 
 
-- - Magnus Rosenius, magro732@opencores.org 
 
 
-- 
 
 
-------------------------------------------------------------------------------
 
 
 
-- 
 
 
-- Copyright (C) 2013 Authors and OPENCORES.ORG 
 
 
-- 
 
 
-- This source file may be used and distributed without 
 
 
-- restriction provided that this copyright statement is not 
 
 
-- removed from the file and that any derivative work contains 
 
 
-- the original copyright notice and the associated disclaimer. 
 
 
-- 
 
 
-- This source file is free software; you can redistribute it 
 
 
-- and/or modify it under the terms of the GNU Lesser General 
 
 
-- Public License as published by the Free Software Foundation; 
 
 
-- either version 2.1 of the License, or (at your option) any 
 
 
-- later version. 
 
 
-- 
 
 
-- This source is distributed in the hope that it will be 
 
 
-- useful, but WITHOUT ANY WARRANTY; without even the implied 
 
 
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
 
 
-- PURPOSE. See the GNU Lesser General Public License for more 
 
 
-- details. 
 
 
-- 
 
 
-- You should have received a copy of the GNU Lesser General 
 
 
-- Public License along with this source; if not, download it 
 
 
-- from http://www.opencores.org/lgpl.shtml 
 
 
-- 
 
 
-------------------------------------------------------------------------------
 
 
 
 
 
 
 
-------------------------------------------------------------------------------
 
-- RioLogicalCommon.
 
-- RioLogicalCommon.
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Ingress:
 
-- Ingress:
 
-- * Removes in-the-middle and trailing CRC.
 
-- * Removes in-the-middle and trailing CRC.
 
-- * Forwards packets to logical-layer handlers depending on ftype and
 
-- * Forwards packets to logical-layer handlers depending on ftype and
Line 80... Line 123... 
-- tt=01
 
-- tt=01
 
-- 0: header(15:0);dest(15:0);
 
-- 0: header(15:0);dest(15:0);
 
-- 1: src(15:0);transaction(3:0)
 
-- 1: src(15:0);transaction(3:0)
 
-- shifter: 16 (48 empty)
 
-- shifter: 16 (48 empty)
 
 
 
 
 
 
 
 
 
 
 
library ieee;
 
 
 
use ieee.std_logic_1164.all;
 
 
 
use ieee.numeric_std.all;
 
 
 
use work.rio_common.all;
 
 
 
 
 
 
 
 
 
 
 
entity RioLogicalCommon is
 
 
 
  port(
 
 
 
    clk : in std_logic;
 
 
 
    areset_n : in std_logic;
 
 
 
    enable : in std_logic;
 
 
 
 
 
 
 
    readFrameEmpty_i : in std_logic;
 
 
 
    readFrame_o : out std_logic;
 
 
 
    readContent_o : out std_logic;
 
 
 
    readContentEnd_i : in std_logic;
 
 
 
    readContentData_i : in std_logic_vector(31 downto 0);
 
 
 
    writeFrameFull_i : in std_logic;
 
 
 
    writeFrame_o : out std_logic;
 
 
 
    writeFrameAbort_o : out std_logic;
 
 
 
    writeContent_o : out std_logic;
 
 
 
    writeContentData_o : out std_logic_vector(31 downto 0);
 
 
 
 
 
 
 
    masterCyc_o : out std_logic;
 
 
 
    masterStb_o : out std_logic;
 
 
 
    masterAdr_o : out std_logic_vector(7 downto 0);
 
 
 
    masterDat_o : out std_logic_vector(31 downto 0);
 
 
 
    masterAck_i : in std_logic;
 
 
 
    slaveCyc_i : in std_logic;
 
 
 
    slaveStb_i : in std_logic;
 
 
 
    slaveDat_i : in std_logic_vector(31 downto 0);
 
 
 
    slaveAck_o : out std_logic;
 
 
 
 
 
 
 
    configStb_o : out std_logic;
 
 
 
    configWe_o : out std_logic;
 
 
 
    configAdr_o : out std_logic_vector(23 downto 0);
 
 
 
    configSel_o : out std_logic_vector(7 downto 0);
 
 
 
    configDat_o : out std_logic_vector(63 downto 0);
 
 
 
    configDat_i : in std_logic_vector(63 downto 0);
 
 
 
    configAck_i : in std_logic);
 
 
 
end entity;
 
 
 
 
 
 
 
 
 
 
 
architecture RioLogicalCommon of RioLogicalCommon is
 
 
 
 
 
 
 
  component RioLogicalCommonIngress is
 
 
 
    port(
 
 
 
      clk : in std_logic;
 
 
 
      areset_n : in std_logic;
 
 
 
 
 
 
 
      readFrameEmpty_i : in std_logic;
 
 
 
      readFrame_o : out std_logic;
 
 
 
      readContent_o : out std_logic;
 
 
 
      readContentEnd_i : in std_logic;
 
 
 
      readContentData_i : in std_logic_vector(31 downto 0);
 
 
 
 
 
 
 
      masterCyc_o : out std_logic;
 
 
 
      masterStb_o : out std_logic;
 
 
 
      masterAdr_o : out std_logic_vector(7 downto 0);
 
 
 
      masterDat_o : out std_logic_vector(31 downto 0);
 
 
 
      masterAck_i : in std_logic);
 
 
 
  end component;
 
 
 
 
 
 
 
  component RioLogicalCommonEgress is
 
 
 
    port(
 
 
 
      clk : in std_logic;
 
 
 
      areset_n : in std_logic;
 
 
 
 
 
 
 
      writeFrameFull_i : in std_logic;
 
 
 
      writeFrame_o : out std_logic;
 
 
 
      writeFrameAbort_o : out std_logic;
 
 
 
      writeContent_o : out std_logic;
 
 
 
      writeContentData_o : out std_logic_vector(31 downto 0);
 
 
 
 
 
 
 
      slaveCyc_i : in std_logic;
 
 
 
      slaveStb_i : in std_logic;
 
 
 
      slaveDat_i : in std_logic_vector(31 downto 0);
 
 
 
      slaveAck_o : out std_logic);
 
 
 
  end component;
 
 
 
 
 
 
 
  component RioLogicalMaintenance is
 
 
 
    port(
 
 
 
      clk : in std_logic;
 
 
 
      areset_n : in std_logic;
 
 
 
      enable : in std_logic;
 
 
 
 
 
 
 
      configStb_o : out std_logic;
 
 
 
      configWe_o : out std_logic;
 
 
 
      configAdr_o : out std_logic_vector(23 downto 0);
 
 
 
      configDat_o : out std_logic_vector(63 downto 0);
 
 
 
      configSel_o : out std_logic_vector(7 downto 0);
 
 
 
      configDat_i : in std_logic_vector(63 downto 0);
 
 
 
      configAck_i : in std_logic;
 
 
 
 
 
 
 
      slaveCyc_i : in std_logic;
 
 
 
      slaveStb_i : in std_logic;
 
 
 
      slaveAdr_i : in std_logic_vector(7 downto 0);
 
 
 
      slaveDat_i : in std_logic_vector(31 downto 0);
 
 
 
      slaveAck_o : out std_logic;
 
 
 
 
 
 
 
      masterCyc_o : out std_logic;
 
 
 
      masterStb_o : out std_logic;
 
 
 
      masterDat_o : out std_logic_vector(31 downto 0);
 
 
 
      masterAck_i : in std_logic);
 
 
 
  end component;
 
 
 
 
 
 
 
begin
 
 
 
 
 
 
 
  masterCyc_o <= masterCyc;
 
 
 
  masterStb_o <= masterStb;
 
 
 
  masterDat_o <= masterDat;
 
 
 
  masterAck_i <= masterAck;
 
 
 
 
 
 
 
  slaveCyc_i <= slaveCyc;
 
 
 
  slaveStb_i <= slaveStb;
 
 
 
  slaveAdr_i <= slaveAdr;
 
 
 
  slaveDat_i <= slaveDat;
 
 
 
  slaveAck_o <= slaveAck or maintenanceAck;
 
 
 
 
 
 
 
  LogicalMaintenance: RioLogicalMaintenance
 
 
 
    port map(
 
 
 
      clk=>clk, areset_n=>areset_n, enable=>enable,
 
 
 
      configStb_o=>configStb_o,
 
 
 
      configWe_o=>configWe_o,
 
 
 
      configAdr_o=>configAdr_o,
 
 
 
      configDat_o=>configDat_o,
 
 
 
      configSel_o=>configSel_o,
 
 
 
      configDat_i=>configDat_i,
 
 
 
      configAck_i=>configAck_i,
 
 
 
      slaveCyc_i=>slaveCyc,
 
 
 
      slaveStb_i=>slaveStb,
 
 
 
      slaveAdr_i=>slaveAdr,
 
 
 
      slaveDat_i=>slaveDat,
 
 
 
      slaveAck_o=>maintenanceAck,
 
 
 
      masterCyc_o=>masterCyc,
 
 
 
      masterStb_o=>masterStb,
 
 
 
      masterDat_o=>masterDat,
 
 
 
      masterAck_i=>masterAck);
 
 
 
 
 
 
 
  -- REMARK: Add interconnect for master signals...
 
 
 
 
 
 
 
  Ingress: RioLogicalCommonIngress
 
 
 
    port map(
 
 
 
      clk=>clk, areset_n=>areset_n,
 
 
 
      readFrameEmpty_i=>readFrameEmpty_i,
 
 
 
      readFrame_o=>readFrame_o,
 
 
 
      readContent_o=>readContent_o,
 
 
 
      readContentEnd_i=>readContentEnd_i,
 
 
 
      readContentData_i=>readContentData_i,
 
 
 
      masterCyc_o=>masterCyc,
 
 
 
      masterStb_o=>masterStb,
 
 
 
      masterAdr_o=>masterAdr,
 
 
 
      masterDat_o=>masterDat,
 
 
 
      masterAck_i=>masterAck);
 
 
 
 
 
 
 
  Egress: RioLogicalCommonEgress
 
 
 
    port map(
 
 
 
      clk=>clk, areset_n=>areset_n,
 
 
 
      writeFrameFull_i=>writeFrameFull_i,
 
 
 
      writeFrame_o=>writeFrame_o,
 
 
 
      writeFrameAbort_o=>writeFrameAbort_o,
 
 
 
      writeContent_o=>writeContent_o,
 
 
 
      writeContentData_o=>writeContentData_o,
 
 
 
      slaveCyc_i=>slaveCyc,
 
 
 
      slaveStb_i=>slaveStb,
 
 
 
      slaveDat_i=>slaveDat,
 
 
 
      slaveAck_o=>slaveAck);
 
 
 
 
 
 
 
end architecture;
 
 
 
 
 
 
 
 
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- RioLogicalCommonIngress.
 
-- RioLogicalCommonIngress.
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- REMARK: Check the destination address to see if it matches the one configured???
 
-- REMARK: Check the destination address to see if it matches the one configured???
 
 
 
-- REMARK: Remove the acknowledge on all accesses on the master bus.
 
 
 
-- REMARK: Add component declarations to riocommon.vhd.
 
library ieee;
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_1164.all;
 
use ieee.numeric_std.all;
 
use ieee.numeric_std.all;
 
use work.rio_common.all;
 
use work.rio_common.all;
 
 
 
 
Line 106... Line 324... 
    readContentData_i : in std_logic_vector(31 downto 0);
 
    readContentData_i : in std_logic_vector(31 downto 0);
 
 
 
 
 
    masterCyc_o : out std_logic;
 
    masterCyc_o : out std_logic;
 
    masterStb_o : out std_logic;
 
    masterStb_o : out std_logic;
 
    masterAdr_o : out std_logic_vector(7 downto 0);
 
    masterAdr_o : out std_logic_vector(7 downto 0);
 
    masterSel_o : out std_logic_vector(3 downto 0);
 
 
 
    masterDat_o : out std_logic_vector(31 downto 0);
 
    masterDat_o : out std_logic_vector(31 downto 0);
 
    masterAck_i : in std_logic);
 
    masterAck_i : in std_logic);
 
end entity;
 
end entity;
 
 
 
 
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- 
-- 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
architecture RioLogicalCommonIngress of RioLogicalCommonIngress is
 
architecture RioLogicalCommonIngress of RioLogicalCommonIngress is
 
 
 
  type StateType is (IDLE,
 
 
 
                     WAIT_HEADER_0, HEADER_0, HEADER_1,
 
 
 
                     SEND_HEADER, SEND_DESTINATION, SEND_SOURCE,
 
 
 
                     FORWARD_SHORT, FORWARD_CRC, FORWARD_LONG, FORWARD_LAST,
 
 
 
                     END_PACKET);
 
 
 
  signal state : StateType;
 
 
 
 
 
 
 
  signal packetPosition : natural range 0 to 32;
 
 
 
  signal packetContent : std_logic_vector(63 downto 0);
 
 
 
 
 
 
 
  signal tt : std_logic_vector(1 downto 0);
 
 
 
  signal ftype : std_logic_vector(3 downto 0);
 
 
 
  signal transaction : std_logic_vector(3 downto 0);
 
 
 
 
 
begin
 
begin
 
 
 
 
 
  process(clk, areset_n)
 
  process(clk, areset_n)
 
  begin
 
  begin
 
    if (areset_n = '0') then
 
    if (areset_n = '0') then
 
 
 
      state <= IDLE;
 
 
 
      packetPosition <= 0;
 
 
 
      packetContent <= (others=>'0');
 
 
 
      tt <= "00";
 
 
 
      ftype <= "0000";
 
 
 
      transaction <= "0000";
 
    elsif (clk'event and clk = '1') then
 
    elsif (clk'event and clk = '1') then
 
      readContent_o <= '0';
 
      readContent_o <= '0';
 
 
 
 
 
      case state is
 
      case state is
 
        when IDLE =>
 
        when IDLE =>
Line 178... Line 413... 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- 
          -- 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          masterStb_o <= '1';
 
          masterStb_o <= '1';
 
          masterAdr_o <= ftype & transaction;
 
          masterAdr_o <= ftype & transaction;
 
          masterSel_o <= x"0011";
 
 
 
          masterDat_o <= x"0000" & packetContent(63 downto 48);
 
          masterDat_o <= x"0000" & packetContent(63 downto 48);
 
          packetContent <= packetContent(47 downto 0) & x"0000";
 
          packetContent <= packetContent(47 downto 0) & x"0000";
 
 
 
 
 
          state <= SEND_DESTINATION;
 
          state <= SEND_DESTINATION;
 
 
 
 
Line 190... Line 424... 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- 
          -- 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          if (masterAck_i = '1') then
 
          if (masterAck_i = '1') then
 
            if (tt = "00") then
 
            if (tt = "00") then
 
              masterSel_o <= x"0001";
 
 
 
              masterDat_o <= x"000000" & packetContent(63 downto 56);
 
              masterDat_o <= x"000000" & packetContent(63 downto 56);
 
              packetContent <= packetContent(55 downto 0) & x"00";
 
              packetContent <= packetContent(55 downto 0) & x"00";
 
            elsif (tt = "01") then
 
            elsif (tt = "01") then
 
              masterSel_o <= x"0011";
 
 
 
              masterDat_o <= x"0000" & packetContent(63 downto 48);
 
              masterDat_o <= x"0000" & packetContent(63 downto 48);
 
              packetContent <= packetContent(31 downto 0) & readContentData_i;
 
              packetContent <= packetContent(31 downto 0) & readContentData_i;
 
              readContent_o <= '1';
 
              readContent_o <= '1';
 
            end if;
 
            end if;
 
 
 
 
Line 209... Line 441... 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- 
          -- 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          if (masterAck_i = '1') then
 
          if (masterAck_i = '1') then
 
            if (tt = "00") then
 
            if (tt = "00") then
 
              masterSel_o <= x"0001";
 
 
 
              masterDat_o <= x"000000" & packetContent(63 downto 56);
 
              masterDat_o <= x"000000" & packetContent(63 downto 56);
 
              packetContent <= packetContent(55 downto 0) & x"00";
 
              packetContent <= packetContent(55 downto 0) & x"00";
 
            elsif (tt = "01") then
 
            elsif (tt = "01") then
 
              masterSel_o <= x"0011";
 
 
 
              masterDat_o <= x"0000" & packetContent(63 downto 48);
 
              masterDat_o <= x"0000" & packetContent(63 downto 48);
 
              packetContent <= packetContent(47 downto 0) & x"0000";
 
              packetContent <= packetContent(47 downto 0) & x"0000";
 
            end if;
 
            end if;
 
 
 
 
 
            state <= FORWARD;
 
            state <= FORWARD_SHORT;
 
          end if;
 
          end if;
 
 
 
 
 
        when FORWARD =>
 
        when FORWARD_SHORT =>
 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- 
          -- 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          if (masterAck_i = '1') then
 
          if (masterAck_i = '1') then
 
            masterSel_o <= x"1111";
 
 
 
            masterDat_o <= packetContent(63 downto 32);
 
            masterDat_o <= packetContent(63 downto 32);
 
 
 
 
 
            packetPosition <= packetPosition + 1;
 
            packetPosition <= packetPosition + 1;
 
 
 
 
 
            -- REMARK: Rewrite depending on tt-field to compensate for
 
 
 
            -- different number of valid bits in the shifter...
 
 
 
            if (packetPosition < 20) then
 
 
 
              packetContent <=
 
              packetContent <=
 
                packetContent(31 downto 0) & readContentData_i;
 
                packetContent(31 downto 0) & readContentData_i;
 
            elsif (packetPosition = 20) then
 
 
 
 
 
            if (readContentEnd_i = '0') then
 
 
 
              if (packetPosition = 20) then
 
 
 
                state <= FORWARD_CRC;
 
 
 
              end if;
 
 
 
 
 
 
 
              readContent_o <= '1';
 
 
 
            else
 
 
 
              readFrame_o <= '1';
 
 
 
              state <= FORWARD_LAST;
 
 
 
            end if;
 
 
 
          end if;
 
 
 
 
 
 
 
        when FORWARD_CRC =>
 
 
 
          ---------------------------------------------------------------------
 
 
 
          -- 
 
 
          ---------------------------------------------------------------------
 
 
 
          if (masterAck_i = '1') then
 
 
 
            masterDat_o <= packetContent(63 downto 32);
 
 
 
 
 
 
 
            packetPosition <= packetPosition + 1;
 
              packetContent <=
 
              packetContent <=
 
                packetContent(31 downto 0) & readContentData_i(15 downto 0) & x"0000";
 
                packetContent(31 downto 0) & readContentData_i(15 downto 0) & x"0000";
 
 
 
 
 
 
 
            if (readContentEnd_i = '0') then
 
 
 
              readContent_o <= '1';
 
 
 
              state <= FORWARD_LONG;
 
            else
 
            else
 
 
 
              readFrame_o <= '1';
 
 
 
              state <= FORWARD_LAST;
 
 
 
            end if;
 
 
 
          end if;
 
 
 
 
 
 
 
        when FORWARD_LONG =>
 
 
 
          ---------------------------------------------------------------------
 
 
 
          -- 
 
 
          ---------------------------------------------------------------------
 
 
 
          if (masterAck_i = '1') then
 
 
 
            masterDat_o <= packetContent(63 downto 32);
 
 
 
 
 
 
 
            packetPosition <= packetPosition + 1;
 
              packetContent <=
 
              packetContent <=
 
                packetContent(15 downto 0) & readContentData_i & x"0000";
 
                packetContent(15 downto 0) & readContentData_i & x"0000";
 
            end if;
 
 
 
 
 
 
 
            if (readContentEnd_i = '0') then
 
            if (readContentEnd_i = '0') then
 
              readContent_o <= '1';
 
              readContent_o <= '1';
 
            else
 
            else
 
              readFrame_o <= '1';
 
              readFrame_o <= '1';
Line 258... Line 519... 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- 
          -- 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- REMARK: The last always contain the CRC?
 
          -- REMARK: The last always contain the CRC?
 
          if (masterAck_i = '1') then
 
          if (masterAck_i = '1') then
 
            masterSel_o <= x"1111";
 
 
 
            masterDat_o <= packetContent(63 downto 32);
 
            masterDat_o <= packetContent(63 downto 32);
 
            state <= END_PACKET;
 
            state <= END_PACKET;
 
          end if;
 
          end if;
 
 
 
 
 
        when END_PACKET =>
 
        when END_PACKET =>
Line 288... Line 548... 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- RioLogicalCommonEgress.
 
-- RioLogicalCommonEgress.
 
-- Only 8-bit and 16-bit deviceId are supported. The first write must contain
 
-- Only 8-bit and 16-bit deviceId are supported. The first write must contain
 
-- the 16-bit header, the second write must contain the destination address and
 
-- the 16-bit header, the second write must contain the destination address and
 
-- the third must contain the source address.
 
-- the third must contain the source address.
 
-- CRC is calculated during the transfer and inserted at byte 81 and 82 and
 
-- CRC is calculated during the transfer and is inserted at byte 81 and 82 and
 
-- appended to the packet when it ends.
 
-- appended to the packet when it ends.
 
-- slaveSelect_i - four bits indicating valid bytes in slaveData_i.
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
library ieee;
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_1164.all;
 
use ieee.numeric_std.all;
 
use ieee.numeric_std.all;
 
use work.rio_common.all;
 
use work.rio_common.all;
Line 313... Line 572... 
    writeContent_o : out std_logic;
 
    writeContent_o : out std_logic;
 
    writeContentData_o : out std_logic_vector(31 downto 0);
 
    writeContentData_o : out std_logic_vector(31 downto 0);
 
 
 
 
 
    slaveCyc_i : in std_logic;
 
    slaveCyc_i : in std_logic;
 
    slaveStb_i : in std_logic;
 
    slaveStb_i : in std_logic;
 
    slaveSel_i : in std_logic_vector(3 downto 0);
 
 
 
    slaveDat_i : in std_logic_vector(31 downto 0);
 
    slaveDat_i : in std_logic_vector(31 downto 0);
 
    slaveAck_o : out std_logic);
 
    slaveAck_o : out std_logic);
 
end entity;
 
end entity;
 
 
 
 
 
 
 
 
Line 331... Line 589... 
      d_i : in  std_logic_vector(15 downto 0);
 
      d_i : in  std_logic_vector(15 downto 0);
 
      crc_i : in  std_logic_vector(15 downto 0);
 
      crc_i : in  std_logic_vector(15 downto 0);
 
      crc_o : out std_logic_vector(15 downto 0));
 
      crc_o : out std_logic_vector(15 downto 0));
 
  end component;
 
  end component;
 
 
 
 
 
 
 
  type StateType is (IDLE,
 
 
 
                     HEADER_GET, HEADER_ACK,
 
 
 
                     DESTINATION_GET, DESTINATION_ACK,
 
 
 
                     SOURCE_GET, SOURCE_ACK,
 
 
 
                     CONTENT_GET, CONTENT_ACK,
 
 
 
                     CRC_APPEND, SEND_FRAME,
 
 
 
                     RESTART_FRAME, WAIT_UPDATE);
 
 
 
  signal state : StateType;
 
 
 
  signal packetPosition : natural range 0 to 31;
 
 
 
  signal halfWordPending : std_logic;
 
 
 
  signal halfWord : std_logic_vector(15 downto 0);
 
 
 
 
 
 
 
  signal header : std_logic_vector(15 downto 0);
 
 
 
  signal tt : std_logic_vector(1 downto 0);
 
 
 
  signal dstAddr : std_logic_vector(31 downto 0);
 
 
 
  signal srcAddr : std_logic_vector(31 downto 0);
 
 
 
 
 
  signal crc16Current, crc16Temp, crc16Next: std_logic_vector(15 downto 0);
 
  signal crc16Current, crc16Temp, crc16Next: std_logic_vector(15 downto 0);
 
 
 
 
 
begin
 
begin
 
 
 
 
 
  process(clk, areset_n)
 
  process(clk, areset_n)
 
  begin
 
  begin
 
    if (areset_n = '0') then
 
    if (areset_n = '0') then
 
 
 
      state <= IDLE;
 
      crc16Current <= x"0000";
 
      crc16Current <= x"0000";
 
      writeContentData <= (others=>'0');
 
      writeContentData <= (others=>'0');
 
    elsif (clk'event and clk = '1') then
 
    elsif (clk'event and clk = '1') then
 
      writeContent_o <= '0';
 
      writeContent_o <= '0';
 
      writeFrame_o <= '0';
 
      writeFrame_o <= '0';
Line 355... Line 631... 
          if (writeFrameFull_i = '0') then
 
          if (writeFrameFull_i = '0') then
 
            state <= HEADER_GET;
 
            state <= HEADER_GET;
 
            crc16Current <= x"ffff";
 
            crc16Current <= x"ffff";
 
          end if;
 
          end if;
 
 
 
 
 
        when GET_HEADER =>
 
        when HEADER_GET =>
 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- 
          -- 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          if ((slaveCyc_i = '1') and (slaveStb_i = '1')) then
 
          if ((slaveCyc_i = '1') and (slaveStb_i = '1')) then
 
            -- REMARK: Only support the header in one position?
 
            -- REMARK: Only support the header in one position?
Line 625... Line 901... 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- RioLogicalMaintenanceRequest
 
-- RioLogicalMaintenance
 
-- This logical layer module handles ingress maintenance requests.
 
-- This logical layer module handles ingress maintenance requests and converts
 
 
 
-- them into accesses on a Wishbone compatible bus accessing the configuration
 
 
 
-- space.
 
-- Addresses: 0x80 (maint read request) and 0x81 (maint write request).
 
-- Addresses: 0x80 (maint read request) and 0x81 (maint write request).
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
library ieee;
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_1164.all;
 
use ieee.numeric_std.all;
 
use ieee.numeric_std.all;
 
use work.rio_common.all;
 
use work.rio_common.all;
 
 
 
 
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Entity for RioLogicalMaintenanceRequest.
 
-- Entity for RioLogicalMaintenance.
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
entity RioLogicalMaintenanceRequest is
 
entity RioLogicalMaintenance is
 
  generic(
 
 
 
    DEVICE_IDENTITY : std_logic_vector(15 downto 0);
 
 
 
    DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
 
 
 
    DEVICE_REV : std_logic_vector(31 downto 0);
 
 
 
    ASSY_IDENTITY : std_logic_vector(15 downto 0);
 
 
 
    ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
 
 
 
    ASSY_REV : std_logic_vector(15 downto 0);
 
 
 
    DEFAULT_BASE_DEVICE_ID : std_logic_vector(15 downto 0) := x"ffff");
 
 
 
  port(
 
  port(
 
    clk : in std_logic;
 
    clk : in std_logic;
 
    areset_n : in std_logic;
 
    areset_n : in std_logic;
 
 
 
    enable : in std_logic;
 
 
 
 
 
    configStb_o : out std_logic;
 
    configStb_o : out std_logic;
 
    configWe_o : out std_logic;
 
    configWe_o : out std_logic;
 
    configAdr_o : out std_logic_vector(23 downto 0);
 
    configAdr_o : out std_logic_vector(23 downto 0);
 
    configDat_o : out std_logic_vector(63 downto 0);
 
    configDat_o : out std_logic_vector(63 downto 0);
Line 675... Line 946... 
 
 
 
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- 
-- 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
architecture RioLogicalMaintenanceRequest of RioLogicalMaintenanceRequest is
 
architecture RioLogicalMaintenance of RioLogicalMaintenance is
 
  component MemorySinglePort is
 
 
 
    generic(
 
  component MaintenanceRequestInbound is
 
      ADDRESS_WIDTH : natural := 1;
 
    port(
 
      DATA_WIDTH : natural := 1);
 
      clk : in std_logic;
 
 
 
      areset_n : in std_logic;
 
 
 
      enable : in std_logic;
 
 
 
 
 
 
 
      requestReadReady_o : out std_logic;
 
 
 
      requestWriteReady_o : out std_logic;
 
 
 
      requestVc_o : out std_logic;
 
 
 
      requestCrf_o : out std_logic;
 
 
 
      requestPrio_o : out std_logic_vector(1 downto 0);
 
 
 
      requestTt_o : out std_logic_vector(1 downto 0);
 
 
 
      requestDstId_o : out std_logic_vector(31 downto 0);
 
 
 
      requestSrcId_o : out std_logic_vector(31 downto 0);
 
 
 
      requestTid_o : out std_logic_vector(7 downto 0);
 
 
 
      requestOffset_o : out std_logic_vector(21 downto 0);
 
 
 
      requestPayloadSelect_o : out std_logic_vector(7 downto 0);
 
 
 
      requestPayloadLength_o : out std_logic_vector(3 downto 0);
 
 
 
      requestPayloadIndex_i : in std_logic_vector(4 downto 0);
 
 
 
      requestPayload_o : out std_logic_vector(63 downto 0);
 
 
 
      requestDone_i : in std_logic;
 
 
 
 
 
 
 
      slaveCyc_i : in std_logic;
 
 
 
      slaveStb_i : in std_logic;
 
 
 
      slaveAdr_i : in std_logic_vector(7 downto 0);
 
 
 
      slaveDat_i : in std_logic_vector(31 downto 0);
 
 
 
      slaveAck_o : out std_logic);
 
 
 
  end component;
 
 
 
 
 
 
 
  component MaintenanceResponseOutbound is
 
    port(
 
    port(
 
      clk_i : in std_logic;
 
      clk : in std_logic;
 
      enable_i : in std_logic;
 
      areset_n : in std_logic;
 
      writeEnable_i : in std_logic;
 
      enable : in std_logic;
 
      address_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
 
 
 
      data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
 
      responseReadReady_i : in std_logic;
 
      data_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
 
      responseWriteReady_i : in std_logic;
 
 
 
      responseVc_i : in std_logic;
 
 
 
      responseCrf_i : in std_logic;
 
 
 
      responsePrio_i : in std_logic_vector(1 downto 0);
 
 
 
      responseTt_i : in std_logic_vector(1 downto 0);
 
 
 
      responseDstId_i : in std_logic_vector(31 downto 0);
 
 
 
      responseSrcId_i : in std_logic_vector(31 downto 0);
 
 
 
      responseTid_i : in std_logic_vector(7 downto 0);
 
 
 
      responsePayloadLength_i : in std_logic_vector(3 downto 0);
 
 
 
      responsePayloadWrite_i : in std_logic;
 
 
 
      responsePayloadIndex_i : in std_logic_vector(4 downto 0);
 
 
 
      responsePayload_i : in std_logic_vector(63 downto 0);
 
 
 
      responseDone_o : out std_logic;
 
 
 
 
 
 
 
      masterCyc_o : out std_logic;
 
 
 
      masterStb_o : out std_logic;
 
 
 
      masterAdr_o : out std_logic_vector(7 downto 0);
 
 
 
      masterDat_o : out std_logic_vector(31 downto 0);
 
 
 
      masterAck_i : in std_logic);
 
  end component;
 
  end component;
 
 
 
 
 
 
 
  type StateType is (IDLE,
 
 
 
                     CONFIG_READ, CONFIG_READ_RESPONSE,
 
 
 
                     CONFIG_WRITE, CONFIG_WRITE_RESPONSE);
 
 
 
  signal state : StateType;
 
 
 
 
 
 
 
  signal vc : std_logic;
 
 
 
  signal crf : std_logic;
 
 
 
  signal prio : std_logic_vector(1 downto 0);
 
 
 
  signal tt : std_logic_vector(1 downto 0);
 
 
 
  signal dstId : std_logic_vector(31 downto 0);
 
 
 
  signal srcId : std_logic_vector(31 downto 0);
 
 
 
  signal tid : std_logic_vector(7 downto 0);
 
 
 
 
 
 
 
  signal requestReadReady : std_logic;
 
 
 
  signal requestWriteReady : std_logic;
 
 
 
  signal requestOffset : std_logic_vector(21 downto 0);
 
 
 
  signal requestPayloadLength : std_logic_vector(3 downto 0);
 
 
 
  signal requestPayloadIndex : std_logic_vector(4 downto 0);
 
 
 
  signal requestDone : std_logic;
 
 
 
 
 
 
 
  signal responseReadReady : std_logic;
 
 
 
  signal responseWriteRead : std_logic;
 
 
 
  signal responsePayloadLength : std_logic_vector(3 downto 0);
 
 
 
  signal responsePayloadWrite : std_logic;
 
 
 
  signal responsePayloadIndex : std_logic_vector(4 downto 0);
 
 
 
  signal responseDone : std_logic;
 
 
 
 
 
begin
 
begin
 
 
 
 
 
  slaveAck_o <= slaveAck;
 
  -----------------------------------------------------------------------------
 
  MaintenanceRequest: process(clk, areset_n)
 
  -- 
 
 
  -----------------------------------------------------------------------------
 
 
 
  Maintenance: process(clk, areset_n)
 
  begin
 
  begin
 
    if (areset_n = '0') then
 
    if (areset_n = '0') then
 
 
 
 
 
    elsif (clk'event and clk = '1') then
 
    elsif (clk'event and clk = '1') then
 
      case state is
 
      case state is
 
        when WAIT_PACKET =>
 
        when IDLE =>
 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- 
          -- 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          if (slaveCyc_i = '1') then
 
          if (requestReadReady = '1') then
 
            if (slaveAck = '0') then
 
            configStb_o <= '1';
 
              if (slaveStb_i = '1') then
 
            configWe_o <= '0';
 
                if (slaveAddress_i = x"80") then
 
            configAdr_o <= requestOffset;
 
                  -- Maintenance read request.
 
            responsePayloadIndex <= (others=>'0');
 
                  case (packetIndex) is
 
            state <= CONFIG_READ;
 
                    when 0 =>
 
          elsif (requestWriteReady = '1') then
 
                      -- x"0000" & ackid & vc & crf & prio & tt & ftype
 
            configStb_o <= '1';
 
                      header <= slaveDat_i(15 downto 0);
 
            configWe_o <= '1';
 
                    when 1 =>
 
            configAdr_o <= requestOffset;
 
                      -- destId
 
            requestPayloadIndex <= (others=>'0');
 
                      destId <= slaveDat_i;
 
            state <= CONFIG_WRITE;
 
                    when 2 =>
 
 
 
                      -- srcId
 
 
 
                      srcId <= slaveDat_i;
 
 
 
                    when 3 =>
 
 
 
                      -- transaction & rdsize & srcTID & hop & config_offset(20:13)
 
 
 
                      size <= slaveDat_i(27 downto 24);
 
 
 
                      srcTid <= slaveDat_i(23 downto 16);
 
 
 
                      configOffset(20 downto 13) <= slaveDat_i(7 downto 0);
 
 
 
                    when 4 =>
 
 
 
                      -- config_offset(12:0) & wdptr & rsrv & crc(15:0)
 
 
 
                      configOffset(12 downto 0) <= slaveDat_i(31 downto 16);
 
 
 
                      wdptr <= slaveDat_i(18);
 
 
 
                      maintReadComplete <= '1';
 
 
 
                    when others =>
 
 
 
                      -- There should be no more content in a maintenance read request.
 
 
 
                      -- Discard.
 
 
 
                  end case;
 
 
 
                elsif (slaveAddress_i = x"81") then
 
 
 
                  -- Maintenance write request.
 
 
 
                  case (packetIndex) is
 
 
 
                    when 0 =>
 
 
 
                      -- x"0000" & ackid & vc & crf & prio & tt & ftype
 
 
 
                      header <= slaveDat_i(15 downto 0);
 
 
 
                    when 1 =>
 
 
 
                      -- destId
 
 
 
                      destId <= slaveDat_i;
 
 
 
                    when 2 =>
 
 
 
                      -- srcId
 
 
 
                      srcId <= slaveDat_i;
 
 
 
                    when 3 =>
 
 
 
                      -- transaction & wrsize & srcTID & hop & config_offset(20:13)
 
 
 
                      size <= slaveDat_i(27 downto 24);
 
 
 
                      srcTid <= slaveDat_i(23 downto 16);
 
 
 
                      configOffset(20 downto 13) <= slaveDat_i(7 downto 0);
 
 
 
                    when 4 =>
 
 
 
                      -- config_offset(12:0) & wdptr & rsrv & double-word(63:48)
 
 
 
                      configOffset(12 downto 0) <= slaveDat_i(31 downto 16);
 
 
 
                      configData(63 downto 48) <= slaveData_i(15 downto 0);
 
 
 
                      wdptr <= slaveDat_i(18);
 
 
 
                      memoryEnable <= '1';
 
 
 
                      memoryAddress <= 0;
 
 
 
                    when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 =>
 
 
 
                      -- double-word(47:16)
 
 
 
                      configData(47 downto 16) <= slaveData_i;
 
 
 
                    when 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 =>
 
 
 
                      -- double-word(15:0) & double-word(63:48)
 
 
 
                      memoryAddress <= memoryAddress + 1;
 
 
 
                      memoryWrite <= '1';
 
 
 
                      memoryDataIn <= configData(63 downto 16) & slaveData_i(31 downto 16);
 
 
 
                      configData(63 downto 48) <= slaveData_i(15 downto 0);
 
 
 
                      maintWriteComplete <= '1';
 
 
 
                    when others =>
 
 
 
                      -- There should be no more content in a maintenance read request.
 
 
 
                      -- Discard.
 
 
 
                  end case;
 
 
 
                end if;
 
 
 
                slaveAck <= '1';
 
 
 
              end if;
 
 
 
            else
 
 
 
              packetIndex <= packetIndex + 1;
 
 
 
              slaveAck <= '0';
 
 
 
            end if;
 
 
 
          else
 
 
 
            if (maintReadComplete = '1') then
 
 
 
              state <= CONFIG_READ;
 
 
 
              configIterator <= bytes;
 
 
 
              memoryEnable <= '1';
 
 
 
              memoryAddress <= 0;
 
 
 
            end if;
 
 
 
            if (maintWriteComplete = '1') then
 
 
 
              state <= CONFIG_WRITE;
 
 
 
            end if;
 
 
 
            packetIndex <= 0;
 
 
 
            maintReadComplete <= '0';
 
 
 
            maintWriteComplete <= '0';
 
 
 
          end if;
 
          end if;
 
 
 
 
 
        when CONFIG_READ =>
 
        when CONFIG_READ =>
 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- 
          -- 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          configStb_o <= '1';
 
 
 
          configWe_o <= '0';
 
 
 
          configAdr_o <= configOffset;
 
 
 
          configSel_o <= byteLanes;
 
 
 
          configIterator <= configIterator - 1;
 
 
 
          configSpaceState <= CONFIG_READ_ACK;
 
 
 
 
 
 
 
        when CONFIG_READ_ACK =>
 
 
 
          ---------------------------------------------------------------------
 
 
 
          -- 
 
 
          ---------------------------------------------------------------------
 
 
 
          if (configAck_i = '1') then
 
          if (configAck_i = '1') then
 
            memoryAddress <= memoryAddress + 1;
 
            responsePayloadWrite <= '1';
 
            memoryWrite <= '1';
 
            responsePayloadIndex <= responsePayloadIndex + 1;
 
            memoryDataIn <= configSpaceDat_i;
 
 
 
 
 
 
 
            if (configIterator /= 0) then
 
            if (responsePayloadIndex /= requestPayloadLength) then
 
              configAdr_o <= configAdr_o + 1;
 
              configAdr_o <= configAdr_o + 1;
 
              state <= CONFIG_READ;
 
 
 
            else
 
            else
 
 
 
              requestDone <= '1';
 
              configStb_o <= '0';
 
              configStb_o <= '0';
 
              packetIndex <= 0;
 
 
 
              state <= CONFIG_READ_RESPONSE;
 
              state <= CONFIG_READ_RESPONSE;
 
            end if;
 
            end if;
 
          end if;
 
          end if;
 
 
 
 
 
        when CONFIG_READ_RESPONSE =>
 
        when CONFIG_READ_RESPONSE =>
 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- 
          -- 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          masterCyc_o <= '1';
 
          responseReadReady <= '1';
 
          masterStb_o <= '1';
 
          if (responseDone = '1') then
 
          masterDat_o <= header;
 
            state <= IDLE;
 
          packetIndex <= packetIndex + 1;
 
          end if;
 
          state <= CONFIG_READ_RESPONSE_ACK;
 
 
 
 
 
 
 
        when CONFIG_READ_RESPONSE_ACK =>
 
        when CONFIG_WRITE =>
 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- 
          -- 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          if (masterAck_i = '1') then
 
          if (configAck_i = '1') then
 
            masterCyc_o <= '1';
 
            if (responsePayloadIndex /= requestPayloadLength) then
 
            masterStb_o <= '1';
 
              configAdr_o <= configAdr_o + 1;
 
            case (packetIndex) is
 
              requestIndex <= requestIndex + 1;
 
              when 0 =>
 
            else
 
                -- x"0000" & ackid & vc & crf & prio & tt & ftype
 
              requestDone <= '1';
 
                masterDat_o <= header;
 
              configStb_o <= '0';
 
              when 1 =>
 
              state <= CONFIG_READ_RESPONSE;
 
                -- destination is the source.
 
            end if;
 
                masterDat_o <= srcId;
 
 
 
              when 2 =>
 
 
 
                -- source is the destination.
 
 
 
                masterDat_o <= destId;
 
 
 
              when 3 =>
 
 
 
                -- transaction & status & targetTID & hop & reserved(7:0)
 
 
 
                masterDat_o <= "0010" & "0000" & srcTid & x"ff" & x"00";
 
 
 
              when 4 =>
 
 
 
                -- reserved(15:0) & double-word0(63:32)
 
 
 
                masterDat_o <= x"0000" & memoryDataOut(63 downto 32);
 
 
 
              when 5 =>
 
 
 
                masterDat_o <= memoryDataOut(31 downto 0) & x"0000";
 
 
 
              -- REMARK: Add more here to send the full response...
 
 
 
              when others =>
 
 
 
                state <= WAIT_PACKET;
 
 
 
            end case;
 
 
 
            packetIndex <= packetIndex + 1;
 
 
 
          end if;
 
          end if;
 
 
 
 
 
        when CONFIG_WRITE =>
 
        when CONFIG_WRITE_RESPONSE =>
 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- 
          -- 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
 
 
          responseReadReady <= '1';
 
 
 
          if (responseDone = '1') then
 
 
 
            state <= IDLE;
 
 
 
          end if;
 
 
 
 
 
        when others =>
 
        when others =>
 
 
 
 
 
      end case;
 
      end case;
 
    end if;
 
    end if;
 
  end process;
 
  end process;
 
 
 
 
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  --
 
  -- Request packet handler.
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- REMARK: Make this a common component?
 
  RequestInbound: MaintenanceRequestInbound
 
  -- REMARK: Change bytes to double-words?
 
    port map(
 
  process(wdptr, size)
 
      clk=>clk,
 
  begin
 
      areset_n=>areset_n,
 
    case (wdptr & size) is
 
      enable=>enable,
 
      when "00000" =>
 
      requestReadReady_o=>requestReadReady,
 
        bytes <= 1;
 
      requestWriteReady_o=>requestWriteReady,
 
        byteLanes <= "10000000";
 
      requestVc_o=>vc,
 
      when "00001" =>
 
      requestCrf_o=>crf,
 
        bytes <= 1;
 
      requestPrio_o=>prio,
 
        byteLanes <= "01000000";
 
      requestTt_o=>tt,
 
 
 
      requestDstId_o=>dstId,
 
      when "00010" =>
 
      requestSrcId_o=>srcId,
 
        bytes <= 1;
 
      requestTid_o=>requestTid,
 
        byteLanes <= "00100000";
 
      requestOffset_o=>requestOffset,
 
      when "00011" =>
 
      requestPayloadSelect_o=>configSel_o,
 
        bytes <= 1;
 
      requestPayloadLength_o=>requestPayloadLength,
 
        byteLanes <= "00010000";
 
      requestPayloadIndex_i=>requestPayloadIndex,
 
 
 
      requestPayload_o=>configDat_o,
 
      when "10000" =>
 
      requestDone_i=>requestDone,
 
        bytes <= 1;
 
      slaveCyc_i=>slaveCyc_i,
 
        byteLanes <= "00001000";
 
      slaveStb_i=>slaveStb_i,
 
      when "10001" =>
 
      slaveAdr_i=>slaveAdr_i,
 
        bytes <= 1;
 
      slaveDat_i=>slaveDat_i,
 
        byteLanes <= "00000100";
 
      slaveAck_o=>slaveAck_o);
 
 
 
 
 
      when "10010" =>
 
 
 
        bytes <= 1;
 
 
 
        byteLanes <= "00000010";
 
 
 
      when "10011" =>
 
 
 
        bytes <= 1;
 
 
 
        byteLanes <= "00000001";
 
 
 
 
 
 
 
      when "00100" =>
 
 
 
        bytes <= 2;
 
 
 
        byteLanes <= "11000000";
 
 
 
      when "00101" =>
 
 
 
        bytes <= 3;
 
 
 
        byteLanes <= "11100000";
 
 
 
 
 
 
 
      when "00110" =>
 
 
 
        bytes <= 2;
 
 
 
        byteLanes <= "00110000";
 
 
 
      when "00111" =>
 
 
 
        bytes <= 5;
 
 
 
        byteLanes <= "11111000";
 
 
 
 
 
 
 
      when "10100" =>
 
 
 
        bytes <= 2;
 
 
 
        byteLanes <= "00001100";
 
 
 
      when "10101" =>
 
 
 
        bytes <= 3;
 
 
 
        byteLanes <= "00000111";
 
 
 
 
 
 
 
      when "10110" =>
 
 
 
        bytes <= 2;
 
 
 
        byteLanes <= "00000011";
 
 
 
      when "10111" =>
 
 
 
        bytes <= 5;
 
 
 
        byteLanes <= "00011111";
 
 
 
 
 
 
 
      when "01000" =>
 
 
 
        bytes <= 4;
 
 
 
        byteLanes <= "11110000";
 
 
 
      when "11000" =>
 
 
 
        bytes <= 4;
 
 
 
        byteLanes <= "00001111";
 
 
 
 
 
 
 
      when "01001" =>
 
 
 
        bytes <= 6;
 
 
 
        byteLanes <= "11111100";
 
 
 
      when "11001" =>
 
 
 
        bytes <= 6;
 
 
 
        byteLanes <= "00111111";
 
 
 
 
 
 
 
      when "01010" =>
 
 
 
        bytes <= 7;
 
 
 
        byteLanes <= "11111110";
 
 
 
      when "11010" =>
 
 
 
        bytes <= 7;
 
 
 
        byteLanes <= "01111111";
 
 
 
 
 
 
 
      when "01011" =>
 
 
 
        bytes <= 8;
 
 
 
        byteLanes <= "11111111";
 
 
 
      when "11011" =>
 
 
 
        bytes <= 16;
 
 
 
        byteLanes <= "11111111";
 
 
 
 
 
 
 
      when "01100" =>
 
 
 
        bytes <= 32;
 
 
 
        byteLanes <= "11111111";
 
 
 
      when "11100" =>
 
 
 
        bytes <= 64;
 
 
 
        byteLanes <= "11111111";
 
 
 
 
 
 
 
      when "01101" =>
 
 
 
        bytes <= 96;
 
 
 
        byteLanes <= "11111111";
 
 
 
      when "11101" =>
 
 
 
        bytes <= 128;
 
 
 
        byteLanes <= "11111111";
 
 
 
 
 
 
 
      when "01110" =>
 
  -----------------------------------------------------------------------------
 
        bytes <= 160;
 
  -- Response packet handler.
 
        byteLanes <= "11111111";
 
  -----------------------------------------------------------------------------
 
      when "11110" =>
 
  -- Note that the dstId and srcId is flipped since the response should be
 
        bytes <= 192;
 
  -- returned to the source.
 
        byteLanes <= "11111111";
 
  ResponseOutbound: MaintenanceResponseOutbound
 
 
 
    port map(
 
 
 
      clk=>clk, areset_n=>areset_n, enable=>enable,
 
 
 
      responseReadReady_i=>responseReadReady,
 
 
 
      responseWriteReady_i=>responseWriteReady,
 
 
 
      responseVc_i=>vc,
 
 
 
      responseCrf_i=>crf,
 
 
 
      responsePrio_i=>prio,
 
 
 
      responseTt_i=>tt,
 
 
 
      responseDstId_i=>srcId,
 
 
 
      responseSrcId_i=>dstId,
 
 
 
      responseTid_i=>tid,
 
 
 
      responsePayloadLength_i=>responsePayloadLength,
 
 
 
      responsePayloadWrite_i=>responsePayloadWrite,
 
 
 
      responsePayloadIndex_i=>responsePayloadIndex,
 
 
 
      responsePayload_i=>configDat_i,
 
 
 
      responseDone_o=>responseDone,
 
 
 
      masterCyc_o=>masterCyc_o,
 
 
 
      masterStb_o=>masterStb_o,
 
 
 
      masterAdr_o=>masterAdr_o,
 
 
 
      masterDat_o=>masterDat_o,
 
 
 
      masterAck_i=>masterAck_i);
 
 
 
 
 
      when "01111" =>
 
end architecture;
 
        bytes <= 224;
 
 
 
        byteLanes <= "11111111";
 
 
 
      when "11111" =>
 
 
 
        bytes <= 256;
 
 
 
        byteLanes <= "11111111";
 
 
 
 
 
 
 
    end case;
 
 
 
  end process;
 
 
 
 
 
 
 
end architecture;
 
-------------------------------------------------------------------------------
 
 
 
-- 
 
 
-------------------------------------------------------------------------------
 
 
 
library ieee;
 
 
 
use ieee.std_logic_1164.all;
 
 
 
use ieee.numeric_std.all;
 
 
 
use work.rio_common.all;
 
 
 
 
 
 
 
 
 
entity MaintenanceReadRequestInbound is
 
-------------------------------------------------------------------------------
 
 
 
-- 
 
 
-------------------------------------------------------------------------------
 
 
 
entity MaintenanceRequestInbound is
 
  port(
 
  port(
 
    clk : in std_logic;
 
    clk : in std_logic;
 
    areset_n : in std_logic;
 
    areset_n : in std_logic;
 
 
 
    enable : in std_logic;
 
 
 
 
 
 
 
    requestReadReady_o : out std_logic;
 
 
 
    requestWriteReady_o : out std_logic;
 
 
 
    requestVc_o : out std_logic;
 
 
 
    requestCrf_o : out std_logic;
 
 
 
    requestPrio_o : out std_logic_vector(1 downto 0);
 
 
 
    requestTt_o : out std_logic_vector(1 downto 0);
 
 
 
    requestDstId_o : out std_logic_vector(31 downto 0);
 
 
 
    requestSrcId_o : out std_logic_vector(31 downto 0);
 
 
 
    requestTid_o : out std_logic_vector(7 downto 0);
 
 
 
    requestOffset_o : out std_logic_vector(21 downto 0);
 
 
 
    requestPayloadSelect_o : out std_logic_vector(7 downto 0);
 
 
 
    requestPayloadLength_o : out std_logic_vector(3 downto 0);
 
 
 
    requestPayloadIndex_i : in std_logic_vector(4 downto 0);
 
 
 
    requestPayload_o : out std_logic_vector(63 downto 0);
 
 
 
    requestDone_i : in std_logic;
 
 
 
 
 
    slaveCyc_i : in std_logic;
 
    slaveCyc_i : in std_logic;
 
    slaveStb_i : in std_logic;
 
    slaveStb_i : in std_logic;
 
    slaveAdr_i : in std_logic_vector(7 downto 0);
 
    slaveAdr_i : in std_logic_vector(7 downto 0);
 
    slaveDat_i : in std_logic_vector(31 downto 0);
 
    slaveDat_i : in std_logic_vector(31 downto 0);
 
    slaveAck_o : out std_logic;
 
    slaveAck_o : out std_logic);
 
 
 
 
 
    header_o : out std_logic_vector(15 downto 0);
 
 
 
    dstId_o : out std_logic_vector(31 downto 0);
 
 
 
    srcId_o : out std_logic_vector(31 downto 0);
 
 
 
    tid_o : out std_logic_vector(7 downto 0);
 
 
 
    configOffset_o : out std_logic_vector(21 downto 0);
 
 
 
    configLength_o : out std_logic_vector(3 downto 0);
 
 
 
    configSelect_o : out std_logic_vector(7 downto 0);
 
 
 
    ready_o : out std_logic;
 
 
 
    done_i : in std_logic);
 
 
 
end entity;
 
end entity;
 
 
 
 
 
 
 
 
 
architecture MaintenanceReadRequestInbound of MaintenanceReadRequestInbound is
 
-------------------------------------------------------------------------------
 
 
 
-- 
 
 
-------------------------------------------------------------------------------
 
 
 
architecture MaintenanceRequestInbound of MaintenanceRequestInbound is
 
 
 
  component MemorySimpleDualPort
 
 
 
    generic(
 
 
 
      ADDRESS_WIDTH : natural := 1;
 
 
 
      DATA_WIDTH : natural := 1);
 
 
 
    port(
 
 
 
      clkA_i : in std_logic;
 
 
 
      enableA_i : in std_logic;
 
 
 
      addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
 
 
 
      dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
 
 
 
 
 
 
 
      clkB_i : in std_logic;
 
 
 
      enableB_i : in std_logic;
 
 
 
      addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
 
 
 
      dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
 
 
 
  end component;
 
 
 
 
 
 
 
  type StateType is (RECEIVE_PACKET, READY);
 
 
 
  signal state : StateType;
 
 
 
 
 
 
 
  signal slaveAck : std_logic;
 
 
 
  signal maintReadComplete : std_logic;
 
 
 
  signal maintWriteComplete : std_logic;
 
 
 
 
 
 
 
  signal packetIndex : natural range 0 to 33;
 
 
 
  signal requstPayload : std_logic_vector(63 downto 0);
 
 
 
 
 
begin
 
begin
 
 
 
 
 
  ready_o <= maintReadComplete;
 
 
 
  slaveAck_o <= slaveAck;
 
  slaveAck_o <= slaveAck;
 
  MaintenanceReadRequest: process(clk, areset_n)
 
 
 
 
 
  requestReadReady_o <= maintReadComplete;
 
 
 
  requestWriteReady_o <= maintWriteComplete;
 
 
 
 
 
 
 
  MaintenanceRequest: process(clk, areset_n)
 
  begin
 
  begin
 
    if (areset_n = '0') then
 
    if (areset_n = '0') then
 
 
 
      packetIndex <= 0;
 
    elsif (clk'event and clk = '1') then
 
    elsif (clk'event and clk = '1') then
 
      case state is
 
      case state is
 
        when WAIT_PACKET =>
 
        when RECEIVE_PACKET =>
 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- 
          -- This state waits for a new maintenance request packet, receives it
 
 
 
          -- and parses it.
 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          if (slaveCyc_i = '1') then
 
          if (slaveCyc_i = '1') then
 
            if (slaveAck = '0') then
 
            if (slaveAck = '0') then
 
              if (slaveStb_i = '1') then
 
              if (slaveStb_i = '1') then
 
                if (slaveAddress_i = x"80") then
 
                if (slaveAddress_i = x"80") then
 
 
 
                  -------------------------------------------------------------
 
 
 
                  -- Maintenance Read Request packet parser.
 
 
 
                  -------------------------------------------------------------
 
                  case (packetIndex) is
 
                  case (packetIndex) is
 
                    when 0 =>
 
                    when 0 =>
 
                      -- x"0000" & ackid & vc & crf & prio & tt & ftype
 
                      -- x"0000" & ackid & vc & crf & prio & tt & ftype
 
                      header <= slaveDat_i(15 downto 0);
 
                      requestHeader_o <= slaveDat_i(15 downto 0);
 
                      packetIndex <= packetIndex + 1;
 
                      packetIndex <= packetIndex + 1;
 
                    when 1 =>
 
                    when 1 =>
 
                      -- destid
 
                      -- destid
 
                      destId <= slaveDat_i;
 
                      requestDstId_o <= slaveDat_i;
 
                      packetIndex <= packetIndex + 1;
 
                      packetIndex <= packetIndex + 1;
 
                    when 2 =>
 
                    when 2 =>
 
                      -- srcid
 
                      -- srcid
 
                      srcId <= slaveDat_i;
 
                      requestSrcId_o <= slaveDat_i;
 
                      packetIndex <= packetIndex + 1;
 
                      packetIndex <= packetIndex + 1;
 
                    when 3 =>
 
                    when 3 =>
 
                      -- transaction & rdsize & srcTID & hop & config_offset(20:13)
 
                      -- transaction & rdsize & srcTID & hop & config_offset(20:13)
 
                      size <= slaveDat_i(27 downto 24);
 
                      size <= slaveDat_i(27 downto 24);
 
                      srcTid <= slaveDat_i(23 downto 16);
 
                      requestTid_o <= slaveDat_i(23 downto 16);
 
                      configOffset(20 downto 13) <= slaveDat_i(7 downto 0);
 
                      requestOffset_o(20 downto 13) <= slaveDat_i(7 downto 0);
 
                      packetIndex <= packetIndex + 1;
 
                      packetIndex <= packetIndex + 1;
 
                    when 4 =>
 
                    when 4 =>
 
                      -- config_offset(12:0) & wdptr & rsrv & crc(15:0)
 
                      -- config_offset(12:0) & wdptr & rsrv & crc(15:0)
 
                      configOffset(12 downto 0) <= slaveDat_i(31 downto 16);
 
                      requestOffset_o(12 downto 0) <= slaveDat_i(31 downto 16);
 
                      wdptr <= slaveDat_i(18);
 
                      wdptr <= slaveDat_i(18);
 
                      packetIndex <= packetIndex + 1;
 
                      packetIndex <= packetIndex + 1;
 
                      maintReadComplete <= '1';
 
                      maintReadComplete <= '1';
 
                    when others =>
 
                    when others =>
 
                      -- There should be no more content in a maintenance read request.
 
                      -- There should be no more content in a maintenance read request.
 
                      -- Discard.
 
                      -- Discard.
 
                  end case;
 
                  end case;
 
 
 
                elsif (slaveAddress_i = x"81") then
 
 
 
                  -------------------------------------------------------------
 
 
 
                  -- Maintenance Write Request packet parser.
 
 
 
                  -------------------------------------------------------------
 
 
 
                  case (packetIndex) is
 
 
 
                    when 0 =>
 
 
 
                      -- x"0000" & ackid & vc & crf & prio & tt & ftype
 
 
 
                      requestHeader_o <= slaveDat_i(15 downto 0);
 
 
 
                      packetIndex <= packetIndex + 1;
 
 
 
                    when 1 =>
 
 
 
                      -- destId
 
 
 
                      requestDstId_o <= slaveDat_i;
 
 
 
                      packetIndex <= packetIndex + 1;
 
 
 
                    when 2 =>
 
 
 
                      -- srcId
 
 
 
                      requestSrcId_o <= slaveDat_i;
 
 
 
                      packetIndex <= packetIndex + 1;
 
 
 
                    when 3 =>
 
 
 
                      -- transaction & wrsize & srcTID & hop & config_offset(20:13)
 
 
 
                      size <= slaveDat_i(27 downto 24);
 
 
 
                      requestTid_o <= slaveDat_i(23 downto 16);
 
 
 
                      requestOffset_o(20 downto 13) <= slaveDat_i(7 downto 0);
 
 
 
                      packetIndex <= packetIndex + 1;
 
 
 
                    when 4 =>
 
 
 
                      -- config_offset(12:0) & wdptr & rsrv & double-word(63:48)
 
 
 
                      requestOffset_o(12 downto 0) <= slaveDat_i(31 downto 16);
 
 
 
                      requestData(63 downto 48) <= slaveData_i(15 downto 0);
 
 
 
                      wdptr <= slaveDat_i(18);
 
 
 
                      packetIndex <= packetIndex + 1;
 
 
 
                    when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 =>
 
 
 
                      -- double-word(47:16)
 
 
 
                      requestData(47 downto 16) <= slaveData_i;
 
 
 
                      packetIndex <= packetIndex + 1;
 
 
 
                    when 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 32 =>
 
 
 
                      -- double-word(15:0) & double-word(63:48)
 
 
 
                      requestData(63 downto 48) <= slaveData_i(15 downto 0);
 
 
 
                      packetIndex <= packetIndex + 1;
 
 
 
 
 
 
 
                      memoryEnable <= '1';
 
 
 
                      memoryAddress <= memoryAddress + 1;
 
 
 
                      memoryWrite <= '1';
 
 
 
                      memoryDataIn <= requestData(63 downto 16) & slaveData_i(31 downto 16);
 
 
 
                      maintWriteComplete <= '1';
 
 
 
                    when others =>
 
 
 
                      -- There should be no more content in a maintenance write request.
 
 
 
                      -- Discard.
 
 
 
                  end case;
 
                end if;
 
                end if;
 
                slaveAck <= '1';
 
                slaveAck <= '1';
 
              end if;
 
              end if;
 
            else
 
            else
 
 
 
              memoryEnable <= '0';
 
 
 
              memoryWrite <= '0';
 
              slaveAck <= '0';
 
              slaveAck <= '0';
 
            end if;
 
            end if;
 
          else
 
          else
 
            if (maintReadComplete = '1') then
 
            if (maintReadComplete = '1') or (maintWriteComplete = '1') then
 
              state <= READY;
 
              state <= READY;
 
            end if;
 
            end if;
 
            packetIndex <= 0;
 
            packetIndex <= 0;
 
 
 
            memoryAddress <= (others=>'0');
 
          end if;
 
          end if;
 
 
 
 
 
        when READY =>
 
        when READY =>
 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- 
          -- Wait for the handler of the packet to signal that it has been
 
 
 
          -- processed.
 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          if (done_i = '1') then
 
          if (requestDone_i = '1') then
 
            maintReadComplete <= '0';
 
            maintReadComplete <= '0';
 
 
 
            maintWriteComplete <= '0';
 
            state <= WAIT_PACKET;
 
            state <= WAIT_PACKET;
 
          end if;
 
          end if;
 
 
 
 
 
        when others =>
 
        when others =>
 
 
 
 
 
      end case;
 
      end case;
 
    end if;
 
    end if;
 
  end process;
 
  end process;
 
 
 
 
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  --
 
  -- Transformation of rdsize/wrsize into length of access and byte lanes.
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- REMARK: Make this a common component?
 
  requestPayloadLength_o <= doubleWords;
 
  -- REMARK: Change bytes to double-words?
 
  requestPayloadSelect_o <= byteLanes;
 
 
 
 
 
 
 
  -- REMARK: Make this a common component? Can be used in IO-accesses as well.
 
 
 
  -- REMARK: Not all of these are allowed in a maintenance request.
 
  process(wdptr, size)
 
  process(wdptr, size)
 
  begin
 
  begin
 
 
 
    if (areset_n = '0') then
 
 
 
      doubleWords <= (others=>'0');
 
 
 
      byteLanes <= (others=>'0');
 
 
 
    elsif (clk'event and clk = '1') then
 
 
 
      if (maintReadComplete = '1') or (maintWriteComplete = '1') then
 
    case (wdptr & size) is
 
    case (wdptr & size) is
 
      when "00000" =>
 
      when "00000" =>
 
        bytes <= 1;
 
            doubleWords <= 1;
 
        byteLanes <= "10000000";
 
        byteLanes <= "10000000";
 
      when "00001" =>
 
      when "00001" =>
 
        bytes <= 1;
 
            doubleWords <= 1;
 
        byteLanes <= "01000000";
 
        byteLanes <= "01000000";
 
 
 
 
 
      when "00010" =>
 
      when "00010" =>
 
        bytes <= 1;
 
            doubleWords <= 1;
 
        byteLanes <= "00100000";
 
        byteLanes <= "00100000";
 
      when "00011" =>
 
      when "00011" =>
 
        bytes <= 1;
 
            doubleWords <= 1;
 
        byteLanes <= "00010000";
 
        byteLanes <= "00010000";
 
 
 
 
 
      when "10000" =>
 
      when "10000" =>
 
        bytes <= 1;
 
            doubleWords <= 1;
 
        byteLanes <= "00001000";
 
        byteLanes <= "00001000";
 
      when "10001" =>
 
      when "10001" =>
 
        bytes <= 1;
 
            doubleWords <= 1;
 
        byteLanes <= "00000100";
 
        byteLanes <= "00000100";
 
 
 
 
 
      when "10010" =>
 
      when "10010" =>
 
        bytes <= 1;
 
            doubleWords <= 1;
 
        byteLanes <= "00000010";
 
        byteLanes <= "00000010";
 
      when "10011" =>
 
      when "10011" =>
 
        bytes <= 1;
 
            doubleWords <= 1;
 
        byteLanes <= "00000001";
 
        byteLanes <= "00000001";
 
 
 
 
 
      when "00100" =>
 
      when "00100" =>
 
        bytes <= 2;
 
            doubleWords <= 1;
 
        byteLanes <= "11000000";
 
        byteLanes <= "11000000";
 
      when "00101" =>
 
      when "00101" =>
 
        bytes <= 3;
 
            doubleWords <= 1;
 
        byteLanes <= "11100000";
 
        byteLanes <= "11100000";
 
 
 
 
 
      when "00110" =>
 
      when "00110" =>
 
        bytes <= 2;
 
            doubleWords <= 1;
 
        byteLanes <= "00110000";
 
        byteLanes <= "00110000";
 
      when "00111" =>
 
      when "00111" =>
 
        bytes <= 5;
 
            doubleWords <= 1;
 
        byteLanes <= "11111000";
 
        byteLanes <= "11111000";
 
 
 
 
 
      when "10100" =>
 
      when "10100" =>
 
        bytes <= 2;
 
            doubleWords <= 1;
 
        byteLanes <= "00001100";
 
        byteLanes <= "00001100";
 
      when "10101" =>
 
      when "10101" =>
 
        bytes <= 3;
 
            doubleWords <= 1;
 
        byteLanes <= "00000111";
 
        byteLanes <= "00000111";
 
 
 
 
 
      when "10110" =>
 
      when "10110" =>
 
        bytes <= 2;
 
            doubleWords <= 1;
 
        byteLanes <= "00000011";
 
        byteLanes <= "00000011";
 
      when "10111" =>
 
      when "10111" =>
 
        bytes <= 5;
 
            doubleWords <= 1;
 
        byteLanes <= "00011111";
 
        byteLanes <= "00011111";
 
 
 
 
 
      when "01000" =>
 
      when "01000" =>
 
        bytes <= 4;
 
            doubleWords <= 1;
 
        byteLanes <= "11110000";
 
        byteLanes <= "11110000";
 
      when "11000" =>
 
      when "11000" =>
 
        bytes <= 4;
 
            doubleWords <= 1;
 
        byteLanes <= "00001111";
 
        byteLanes <= "00001111";
 
 
 
 
 
      when "01001" =>
 
      when "01001" =>
 
        bytes <= 6;
 
            doubleWords <= 1;
 
        byteLanes <= "11111100";
 
        byteLanes <= "11111100";
 
      when "11001" =>
 
      when "11001" =>
 
        bytes <= 6;
 
            doubleWords <= 1;
 
        byteLanes <= "00111111";
 
        byteLanes <= "00111111";
 
 
 
 
 
      when "01010" =>
 
      when "01010" =>
 
        bytes <= 7;
 
            doubleWords <= 1;
 
        byteLanes <= "11111110";
 
        byteLanes <= "11111110";
 
      when "11010" =>
 
      when "11010" =>
 
        bytes <= 7;
 
            doubleWords <= 1;
 
        byteLanes <= "01111111";
 
        byteLanes <= "01111111";
 
 
 
 
 
      when "01011" =>
 
      when "01011" =>
 
        bytes <= 8;
 
            doubleWords <= 1;
 
        byteLanes <= "11111111";
 
        byteLanes <= "11111111";
 
      when "11011" =>
 
      when "11011" =>
 
        bytes <= 16;
 
            doubleWords <= 2;
 
        byteLanes <= "11111111";
 
        byteLanes <= "11111111";
 
 
 
 
 
      when "01100" =>
 
      when "01100" =>
 
        bytes <= 32;
 
            doubleWords <= 4;
 
        byteLanes <= "11111111";
 
        byteLanes <= "11111111";
 
      when "11100" =>
 
      when "11100" =>
 
        bytes <= 64;
 
            doubleWords <= 8;
 
        byteLanes <= "11111111";
 
        byteLanes <= "11111111";
 
 
 
 
 
      when "01101" =>
 
      when "01101" =>
 
        bytes <= 96;
 
            doubleWords <= 12;
 
        byteLanes <= "11111111";
 
        byteLanes <= "11111111";
 
      when "11101" =>
 
      when "11101" =>
 
        bytes <= 128;
 
            doubleWords <= 16;
 
        byteLanes <= "11111111";
 
        byteLanes <= "11111111";
 
 
 
 
 
      when "01110" =>
 
      when "01110" =>
 
        bytes <= 160;
 
            doubleWords <= 20;
 
        byteLanes <= "11111111";
 
        byteLanes <= "11111111";
 
      when "11110" =>
 
      when "11110" =>
 
        bytes <= 192;
 
            doubleWords <= 24;
 
        byteLanes <= "11111111";
 
        byteLanes <= "11111111";
 
 
 
 
 
      when "01111" =>
 
      when "01111" =>
 
        bytes <= 224;
 
            doubleWords <= 28;
 
        byteLanes <= "11111111";
 
        byteLanes <= "11111111";
 
      when "11111" =>
 
      when "11111" =>
 
        bytes <= 256;
 
            doubleWords <= 32;
 
        byteLanes <= "11111111";
 
        byteLanes <= "11111111";
 
 
 
        end case;
 
 
 
      end if;
 
 
 
    end if;
 
 
 
  end process;
 
 
 
 
 
 
 
  -----------------------------------------------------------------------------
 
 
 
  -- Payload content memory.
 
 
 
  -----------------------------------------------------------------------------
 
 
 
  PayloadMemory: MemorySimpleDualPort
 
 
 
    generic map(ADDRESS_WIDTH=>3, DATA_WIDTH=>64)
 
 
 
    port map(clkA_i=>clk,
 
 
 
             enableA_i=>memoryWrite,
 
 
 
             addressA_i=>memoryAddress,
 
 
 
             dataA_i=>memoryDataIn,
 
 
 
             clkB_i=>clk,
 
 
 
             enableB_i=>enable,
 
 
 
             addressB_i=>requestPayloadIndex_i,
 
 
 
             dataB_o=>requestPayload_o);
 
 
 
 
 
 
 
end architecture;
 
 
 
 
 
 
 
 
 
 
 
-------------------------------------------------------------------------------
 
 
 
-- 
 
 
-------------------------------------------------------------------------------
 
 
 
library ieee;
 
 
 
use ieee.std_logic_1164.all;
 
 
 
use ieee.numeric_std.all;
 
 
 
use work.rio_common.all;
 
 
 
 
 
 
 
-------------------------------------------------------------------------------
 
 
 
-- 
 
 
-------------------------------------------------------------------------------
 
 
 
-- REMARK: Add handler for maintenance response with error also...
 
 
 
entity MaintenanceResponseOutbound is
 
 
 
  port(
 
 
 
    clk : in std_logic;
 
 
 
    areset_n : in std_logic;
 
 
 
    enable : in std_logic;
 
 
 
 
 
 
 
    responseReadReady_i : in std_logic;
 
 
 
    responseWriteReady_i : in std_logic;
 
 
 
    responseVc_i : in std_logic;
 
 
 
    responseCrf_i : in std_logic;
 
 
 
    responsePrio_i : in std_logic_vector(1 downto 0);
 
 
 
    responseTt_i : in std_logic_vector(1 downto 0);
 
 
 
    responseDstId_i : in std_logic_vector(31 downto 0);
 
 
 
    responseSrcId_i : in std_logic_vector(31 downto 0);
 
 
 
    responseTid_i : in std_logic_vector(7 downto 0);
 
 
 
    responsePayloadLength_i : in std_logic_vector(3 downto 0);
 
 
 
    responsePayloadWrite_i : in std_logic;
 
 
 
    responsePayloadIndex_i : in std_logic_vector(4 downto 0);
 
 
 
    responsePayload_i : in std_logic_vector(63 downto 0);
 
 
 
    responseDone_o : out std_logic;
 
 
 
 
 
 
 
    masterCyc_o : out std_logic;
 
 
 
    masterStb_o : out std_logic;
 
 
 
    masterAdr_o : out std_logic_vector(7 downto 0);
 
 
 
    masterDat_o : out std_logic_vector(31 downto 0);
 
 
 
    masterAck_i : in std_logic);
 
 
 
end entity;
 
 
 
 
 
 
 
 
 
 
 
-------------------------------------------------------------------------------
 
 
 
-- 
 
 
-------------------------------------------------------------------------------
 
 
 
architecture MaintenanceResponseOutbound of MaintenanceResponseOutbound is
 
 
 
  component MemorySimpleDualPort
 
 
 
    generic(
 
 
 
      ADDRESS_WIDTH : natural := 1;
 
 
 
      DATA_WIDTH : natural := 1);
 
 
 
    port(
 
 
 
      clkA_i : in std_logic;
 
 
 
      enableA_i : in std_logic;
 
 
 
      addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
 
 
 
      dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
 
 
 
 
 
 
 
      clkB_i : in std_logic;
 
 
 
      enableB_i : in std_logic;
 
 
 
      addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
 
 
 
      dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
 
 
 
  end component;
 
 
 
 
 
 
 
  type StateType is (WAIT_PACKET,
 
 
 
                     READ_RESPONSE, WRITE_RESPONSE,
 
 
 
                     RESPONSE_DONE);
 
 
 
  signal state : StateType;
 
 
 
 
 
 
 
  signal packetIndex : natural range 0 to 33;
 
 
 
  signal responseHeader : std_logic_vector(15 downto 0);
 
 
 
  signal responsePayload : std_logic_vector(63 downto 0);
 
 
 
 
 
 
 
  signal memoryEnable : std_logic;
 
 
 
  signal memoryAddress : std_logic_vector(4 downto 0);
 
 
 
  signal memoryDataRead : std_logic_vector(63 downto 0);
 
 
 
 
 
 
 
begin
 
 
 
 
 
 
 
  responseHeader <=
 
 
 
    x"0000" & "000000" & responseVc_i & responseCrf_i &
 
 
 
    responsePrio_i & responseTt_i & x"8";
 
 
 
 
 
 
 
  slaveAck_o <= slaveAck;
 
 
 
 
 
 
 
  MaintenanceResponse: process(clk, areset_n)
 
 
 
  begin
 
 
 
    if (areset_n = '0') then
 
 
 
 
 
 
 
    elsif (clk'event and clk = '1') then
 
 
 
      if (responseReadReady_i = '1') or (responseWriteReady_i = '1') then
 
 
 
        case state is
 
 
 
          when WAIT_PACKET =>
 
 
 
            -------------------------------------------------------------------
 
 
 
            -- 
 
 
            -------------------------------------------------------------------
 
 
 
            if (responseReadReady_i = '1') then
 
 
 
              masterCyc_o <= '1';
 
 
 
              masterStb_o <= '1';
 
 
 
              masterDat_o <= responseHeader;
 
 
 
              packetIndex <= 1;
 
 
 
              memoryEnable <= '1';
 
 
 
              state <= READ_RESPONSE;
 
 
 
            elsif (responseWriteReady_i = '1') then
 
 
 
              masterCyc_o <= '1';
 
 
 
              masterStb_o <= '1';
 
 
 
              masterDat_o <= responseHeader;
 
 
 
              packetIndex <= 1;
 
 
 
              state <= WRITE_RESPONSE;
 
 
 
            end if;
 
 
 
 
 
 
 
          when READ_RESPONSE =>
 
 
 
            ---------------------------------------------------------------------
 
 
 
            -- 
 
 
            ---------------------------------------------------------------------
 
 
 
            if (masterAck_i = '1') then
 
 
 
              if (packetIndex = responseLength_i) then
 
 
 
                masterCyc_o <= '0';
 
 
 
                masterStb_o <= '0';
 
 
 
                state <= RESPONSE_DONE;
 
 
 
              else
 
 
 
                case (packetIndex) is
 
 
 
                  when 1 =>
 
 
 
                    -- destination
 
 
 
                    masterDat_o <= responseDstId_i;
 
 
 
                    packetIndex <= packetIndex + 1;
 
 
 
                  when 2 =>
 
 
 
                    -- source 
 
 
                    masterDat_o <= responseSrcId_i;
 
 
 
                    packetIndex <= packetIndex + 1;
 
 
 
                  when 3 =>
 
 
 
                    -- transaction & status & targetTID & hop & reserved(7:0)
 
 
 
                    masterDat_o <= "0010" & "0000" & responseTid_i & x"ff" & x"00";
 
 
 
                    responsePayload <= memoryDataRead;
 
 
 
                    memoryAddress <= memoryAddress + 1;
 
 
 
                    packetIndex <= packetIndex + 1;
 
 
 
                  when 4 =>
 
 
 
                    -- reserved(15:0) & double-wordN(63:48)
 
 
 
                    masterDat_o <= x"0000" & responsePayload(63 downto 48);
 
 
 
                    packetIndex <= packetIndex + 1;
 
 
 
                  when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 | 33 =>
 
 
 
                    -- double-wordN(47:16)
 
 
 
                    masterDat_o <= responsePayload(47 downto 16);
 
 
 
                    packetIndex <= packetIndex + 1;
 
 
 
                  when 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 32 | 34 =>
 
 
 
                    -- double-wordN(15:0) & double-wordN(63:32)
 
 
 
                    masterDat_o <= responsePayload(15 downto 0) & responsePayload_i(63 downto 48);
 
 
 
                    responsePayload <= memoryDataRead;
 
 
 
                    memoryAddress <= memoryAddress + 1;
 
 
 
                    packetIndex <= packetIndex + 1;
 
 
 
                  when others =>
 
 
 
                    -- Unallowed response length.
 
 
 
                    -- Dont do anything.
 
 
 
                end case;
 
 
 
              end if;
 
 
 
            end if;
 
 
 
 
 
 
 
          when WRITE_RESPONSE =>
 
 
 
            ---------------------------------------------------------------------
 
 
 
            -- 
 
 
            ---------------------------------------------------------------------
 
 
 
            if (masterAck_i = '1') then
 
 
 
              case (packetIndex) is
 
 
 
                when 1 =>
 
 
 
                  -- destination
 
 
 
                  masterDat_o <= responseDstId_i;
 
 
 
                  packetIndex <= packetIndex + 1;
 
 
 
                when 2 =>
 
 
 
                  -- source 
 
 
                  masterDat_o <= responseSrcId_i;
 
 
 
                  packetIndex <= packetIndex + 1;
 
 
 
                when 3 =>
 
 
 
                  -- transaction & status & targetTID & hop & reserved(7:0)
 
 
 
                  masterDat_o <= "0010" & "0000" & responseTid_i & x"ff" & x"00";
 
 
 
                  responsePayload <= memoryDataRead;
 
 
 
                  packetIndex <= packetIndex + 1;
 
 
 
                when 4 =>
 
 
 
                  -- reserved(15:0) & crc(15:0)
 
 
 
                  masterDat_o <= x"00000000";
 
 
 
                  packetIndex <= packetIndex + 1;
 
 
 
                when others =>
 
 
 
                  -- Response packet has been completed.
 
 
 
                  masterCyc_o <= '0';
 
 
 
                  masterStb_o <= '0';
 
 
 
                  state <= RESPONSE_DONE;
 
 
 
              end case;
 
 
 
            end if;
 
 
 
 
 
 
 
          when RESPONSE_DONE =>
 
 
 
            ---------------------------------------------------------------------
 
 
 
            -- 
 
 
            ---------------------------------------------------------------------
 
 
 
            memoryEnable <= '0';
 
 
 
            if (responseRead_i = '0') and (responseWrite = '0') then
 
 
 
              state <= WAIT_PACKET;
 
 
 
              responseDone_o <= '0';
 
 
 
            else
 
 
 
              responseDone_o <= '1';
 
 
 
            end if;
 
 
 
 
 
 
 
          when others =>
 
 
 
            ---------------------------------------------------------------------
 
 
 
            -- 
 
 
            ---------------------------------------------------------------------
 
 
 
            state <= WAIT_PACKET;
 
 
 
 
 
    end case;
 
    end case;
 
 
 
      end if;
 
 
 
    end if;
 
  end process;
 
  end process;
 
 
 
 
 
 
 
  -----------------------------------------------------------------------------
 
 
 
  -- Payload content memory.
 
 
 
  -----------------------------------------------------------------------------
 
 
 
  PayloadMemory: MemorySimpleDualPort
 
 
 
    generic map(ADDRESS_WIDTH=>5, DATA_WIDTH=>64)
 
 
 
    port map(clkA_i=>clk,
 
 
 
             enableA_i=>responsePayloadWrite_i,
 
 
 
             addressA_i=>responsePayloadIndex_i,
 
 
 
             dataA_i=>responsePayload_i,
 
 
 
             clkB_i=>clk,
 
 
 
             enableB_i=>memoryEnable,
 
 
 
             addressB_i=>memoryAddress,
 
 
 
             dataB_o=>memoryDataRead);
 
 
 
 
 
end architecture;
 
end architecture;
 
 
 
 
 
 No newline at end of file
 
 No newline at end of file

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