| Line 8... |
Line 8... |
-- Description
|
-- Description
|
-- Containing a bridge between a RapidIO network and a Wishbone bus. Packets
|
-- Containing a bridge between a RapidIO network and a Wishbone bus. Packets
|
-- NWRITE, NWRITER and NREAD are currently supported.
|
-- NWRITE, NWRITER and NREAD are currently supported.
|
--
|
--
|
-- To Do:
|
-- To Do:
|
-- -
|
-- REMARK: Set the stb_o to '0' in between read accesses to conform better to a
|
|
-- block transfer in the Wishbone standard.
|
|
-- REMARK: Clean up cyc-signals, only stb-signals are needed (between
|
|
-- RioLogicalCommon and the packet handlers).
|
|
-- REMARK: Add support for the lock_o to be sure to transfer all the packet
|
|
-- content atomically?
|
|
-- REMARK: Add support for EXTENDED_ADDRESS.
|
|
-- REMARK: Use the baseDeviceId when sending packets? Currently, all responses
|
|
-- are sent with destination<->source exchanged so the baseDeviceId is not
|
|
-- needed.
|
|
-- REMARK: Support inbound data with full bandwidth, not just half, applies to
|
|
-- RioLogicalCommon and the packet handlers.
|
|
-- REMARK: Move the packet handlers to seperate files.
|
|
-- REMARK: Increase the priority of the response-packet when sent?
|
|
-- REMARK: Implement error indications if erronous packets are received.
|
|
-- REMARK: Implement error indications if err_i is received on the Wishbone bus.
|
|
-- REMARK: Add support for extended features to dynamically configure the status
|
|
-- from the port this block is connected to. Needed for the discovered- and
|
|
-- masterEnable-bits.
|
|
-- REMARK: Add support for outbound doorbells connected to interrupt input pins.
|
--
|
--
|
-- Author(s):
|
-- Author(s):
|
-- - Magnus Rosenius, magro732@opencores.org
|
-- - Magnus Rosenius, magro732@opencores.org
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
| Line 40... |
Line 59... |
-- Public License along with this source; if not, download it
|
-- Public License along with this source; if not, download it
|
-- from http://www.opencores.org/lgpl.shtml
|
-- from http://www.opencores.org/lgpl.shtml
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- RioWbBridge.
|
-- RioWbBridge.
|
|
-- This block acts as an RapidIO endpoint and converts packets into Wishbone
|
|
-- accesses.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- REMARK: Add support for EXTENDED_ADDRESS...
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
use work.rio_common.all;
|
use work.rio_common.all;
|
|
|
| Line 115... |
Line 136... |
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
length_o : out std_logic_vector(4 downto 0);
|
length_o : out std_logic_vector(4 downto 0);
|
select_o : out std_logic_vector(7 downto 0);
|
select_o : out std_logic_vector(7 downto 0);
|
done_i : in std_logic;
|
done_i : in std_logic;
|
|
|
slaveCyc_i : in std_logic;
|
inboundCyc_i : in std_logic;
|
slaveStb_i : in std_logic;
|
inboundStb_i : in std_logic;
|
slaveAdr_i : in std_logic_vector(7 downto 0);
|
inboundAdr_i : in std_logic_vector(7 downto 0);
|
slaveDat_i : in std_logic_vector(31 downto 0);
|
inboundDat_i : in std_logic_vector(31 downto 0);
|
slaveAck_o : out std_logic);
|
inboundAck_o : out std_logic);
|
end component;
|
end component;
|
|
|
component WriteClassInbound is
|
component WriteClassInbound is
|
generic(
|
generic(
|
EXTENDED_ADDRESS : natural range 0 to 2 := 0);
|
EXTENDED_ADDRESS : natural range 0 to 2 := 0);
|
| Line 131... |
Line 152... |
clk : in std_logic;
|
clk : in std_logic;
|
areset_n : in std_logic;
|
areset_n : in std_logic;
|
enable : in std_logic;
|
enable : in std_logic;
|
|
|
ready_o : out std_logic;
|
ready_o : out std_logic;
|
|
responseNeeded_o : out std_logic;
|
vc_o : out std_logic;
|
vc_o : out std_logic;
|
crf_o : out std_logic;
|
crf_o : out std_logic;
|
prio_o : out std_logic_vector(1 downto 0);
|
prio_o : out std_logic_vector(1 downto 0);
|
tt_o : out std_logic_vector(1 downto 0);
|
tt_o : out std_logic_vector(1 downto 0);
|
dstId_o : out std_logic_vector(31 downto 0);
|
dstId_o : out std_logic_vector(31 downto 0);
|
| Line 146... |
Line 168... |
payloadRead_i : in std_logic;
|
payloadRead_i : in std_logic;
|
payloadIndex_i : in std_logic_vector(4 downto 0);
|
payloadIndex_i : in std_logic_vector(4 downto 0);
|
payload_o : out std_logic_vector(63 downto 0);
|
payload_o : out std_logic_vector(63 downto 0);
|
done_i : in std_logic;
|
done_i : in std_logic;
|
|
|
slaveCyc_i : in std_logic;
|
inboundCyc_i : in std_logic;
|
slaveStb_i : in std_logic;
|
inboundStb_i : in std_logic;
|
slaveAdr_i : in std_logic_vector(7 downto 0);
|
inboundAdr_i : in std_logic_vector(7 downto 0);
|
slaveDat_i : in std_logic_vector(31 downto 0);
|
inboundDat_i : in std_logic_vector(31 downto 0);
|
slaveAck_o : out std_logic);
|
inboundAck_o : out std_logic);
|
end component;
|
end component;
|
|
|
component ResponseClassOutbound is
|
component ResponseClassOutbound is
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
| Line 175... |
Line 197... |
payloadWrite_i : in std_logic;
|
payloadWrite_i : in std_logic;
|
payloadIndex_i : in std_logic_vector(4 downto 0);
|
payloadIndex_i : in std_logic_vector(4 downto 0);
|
payload_i : in std_logic_vector(63 downto 0);
|
payload_i : in std_logic_vector(63 downto 0);
|
done_o : out std_logic;
|
done_o : out std_logic;
|
|
|
masterCyc_o : out std_logic;
|
outboundCyc_o : out std_logic;
|
masterStb_o : out std_logic;
|
outboundStb_o : out std_logic;
|
masterDat_o : out std_logic_vector(31 downto 0);
|
outboundDat_o : out std_logic_vector(31 downto 0);
|
masterAck_i : in std_logic);
|
outboundAck_i : in std_logic);
|
|
end component;
|
|
|
|
component RioLogicalMaintenance is
|
|
port(
|
|
clk : in std_logic;
|
|
areset_n : in std_logic;
|
|
enable : in std_logic;
|
|
|
|
configStb_o : out std_logic;
|
|
configWe_o : out std_logic;
|
|
configAdr_o : out std_logic_vector(21 downto 0);
|
|
configDat_o : out std_logic_vector(31 downto 0);
|
|
configDat_i : in std_logic_vector(31 downto 0);
|
|
configAck_i : in std_logic;
|
|
|
|
inboundCyc_i : in std_logic;
|
|
inboundStb_i : in std_logic;
|
|
inboundAdr_i : in std_logic_vector(7 downto 0);
|
|
inboundDat_i : in std_logic_vector(31 downto 0);
|
|
inboundAck_o : out std_logic;
|
|
|
|
outboundCyc_o : out std_logic;
|
|
outboundStb_o : out std_logic;
|
|
outboundDat_o : out std_logic_vector(31 downto 0);
|
|
outboundAck_i : in std_logic);
|
end component;
|
end component;
|
|
|
component RioLogicalCommon is
|
component RioLogicalCommon is
|
|
generic(
|
|
PORTS : natural);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
areset_n : in std_logic;
|
areset_n : in std_logic;
|
enable : in std_logic;
|
enable : in std_logic;
|
|
|
| Line 199... |
Line 248... |
writeFrame_o : out std_logic;
|
writeFrame_o : out std_logic;
|
writeFrameAbort_o : out std_logic;
|
writeFrameAbort_o : out std_logic;
|
writeContent_o : out std_logic;
|
writeContent_o : out std_logic;
|
writeContentData_o : out std_logic_vector(31 downto 0);
|
writeContentData_o : out std_logic_vector(31 downto 0);
|
|
|
masterCyc_o : out std_logic;
|
inboundCyc_o : out std_logic;
|
masterStb_o : out std_logic;
|
inboundStb_o : out std_logic;
|
masterAdr_o : out std_logic_vector(7 downto 0);
|
inboundAdr_o : out std_logic_vector(7 downto 0);
|
masterDat_o : out std_logic_vector(31 downto 0);
|
inboundDat_o : out std_logic_vector(31 downto 0);
|
masterAck_i : in std_logic;
|
inboundAck_i : in std_logic;
|
|
|
slaveCyc_i : in std_logic;
|
outboundCyc_i : in std_logic_vector(PORTS-1 downto 0);
|
slaveStb_i : in std_logic;
|
outboundStb_i : in std_logic_vector(PORTS-1 downto 0);
|
slaveDat_i : in std_logic_vector(31 downto 0);
|
outboundDat_i : in std_logic_vector(32*PORTS-1 downto 0);
|
slaveAck_o : out std_logic);
|
outboundAck_o : out std_logic_vector(PORTS-1 downto 0));
|
end component;
|
end component;
|
|
|
|
constant PORTS : natural := 2;
|
|
|
type StateType is (IDLE,
|
type StateType is (IDLE,
|
REQUEST_CLASS, REQUEST_CLASS_RESPONSE,
|
REQUEST_CLASS, REQUEST_CLASS_RESPONSE,
|
WRITE_CLASS, WRITE_CLASS_RESPONSE);
|
WRITE_CLASS, WRITE_CLASS_ACCESS, WRITE_CLASS_ACK, WRITE_CLASS_RESPONSE);
|
signal state : StateType;
|
signal state : StateType;
|
|
|
signal adr : std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
signal adr : std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
signal datOut : std_logic_vector(63 downto 0);
|
signal datOut : std_logic_vector(63 downto 0);
|
|
|
| Line 237... |
Line 288... |
signal requestSelect : std_logic_vector(7 downto 0);
|
signal requestSelect : std_logic_vector(7 downto 0);
|
signal requestDone : std_logic;
|
signal requestDone : std_logic;
|
signal requestAck : std_logic;
|
signal requestAck : std_logic;
|
|
|
signal writeReady : std_logic;
|
signal writeReady : std_logic;
|
|
signal writeResponse : std_logic;
|
signal writeVc : std_logic;
|
signal writeVc : std_logic;
|
signal writeCrf : std_logic;
|
signal writeCrf : std_logic;
|
signal writePrio : std_logic_vector(1 downto 0);
|
signal writePrio : std_logic_vector(1 downto 0);
|
signal writeTt : std_logic_vector(1 downto 0);
|
signal writeTt : std_logic_vector(1 downto 0);
|
signal writeDstId : std_logic_vector(31 downto 0);
|
signal writeDstId : std_logic_vector(31 downto 0);
|
| Line 264... |
Line 316... |
signal responseError : std_logic;
|
signal responseError : std_logic;
|
signal responsePayloadPresent : std_logic;
|
signal responsePayloadPresent : std_logic;
|
signal responsePayload : std_logic_vector(63 downto 0);
|
signal responsePayload : std_logic_vector(63 downto 0);
|
signal responseDone : std_logic;
|
signal responseDone : std_logic;
|
|
|
|
signal configStb : std_logic;
|
|
signal configWe : std_logic;
|
|
signal configAdr : std_logic_vector(21 downto 0);
|
|
signal configAdrByte : std_logic_vector(23 downto 0);
|
|
signal configDatWrite : std_logic_vector(31 downto 0);
|
|
signal configDatRead : std_logic_vector(31 downto 0);
|
|
signal configAck : std_logic;
|
|
signal maintenanceAck : std_logic;
|
|
|
signal inboundCyc : std_logic;
|
signal inboundCyc : std_logic;
|
signal inboundStb : std_logic;
|
signal inboundStb : std_logic;
|
signal inboundAdr : std_logic_vector(7 downto 0);
|
signal inboundAdr : std_logic_vector(7 downto 0);
|
signal inboundDat : std_logic_vector(31 downto 0);
|
signal inboundDat : std_logic_vector(31 downto 0);
|
signal inboundAck : std_logic;
|
signal inboundAck : std_logic;
|
|
|
signal outboundCyc : std_logic;
|
signal outboundCyc : std_logic_vector(PORTS-1 downto 0);
|
signal outboundStb : std_logic;
|
signal outboundStb : std_logic_vector(PORTS-1 downto 0);
|
signal outboundDat : std_logic_vector(31 downto 0);
|
signal outboundDat : std_logic_vector(32*PORTS-1 downto 0);
|
signal outboundAck : std_logic;
|
signal outboundAck : std_logic_vector(PORTS-1 downto 0);
|
|
|
-- signal configStb : std_logic;
|
|
-- signal configWe : std_logic;
|
|
-- signal configAdr : std_logic_vector(23 downto 0);
|
|
-- signal configDatWrite : std_logic_vector(31 downto 0);
|
|
-- signal configDatRead : std_logic_vector(31 downto 0);
|
|
-- signal configAck : std_logic;
|
|
|
|
-- signal componentTag : std_logic_vector(31 downto 0);
|
|
-- signal baseDeviceId : std_logic_vector(15 downto 0) := DEFAULT_BASE_DEVICE_ID;
|
|
-- signal hostBaseDeviceIdLocked : std_logic;
|
|
-- signal hostBaseDeviceId : std_logic_vector(15 downto 0) := (others => '1');
|
|
|
|
begin
|
begin
|
|
|
responseVc <= requestVc when (responsePayloadPresent = '1') else writeVc;
|
responseVc <= requestVc when (responsePayloadPresent = '1') else writeVc;
|
responseCrf <= requestCrf when (responsePayloadPresent = '1') else writeCrf;
|
responseCrf <= requestCrf when (responsePayloadPresent = '1') else writeCrf;
|
| Line 351... |
Line 400... |
payloadIndex <= (others=>'0');
|
payloadIndex <= (others=>'0');
|
|
|
responsePayloadPresent <= '1';
|
responsePayloadPresent <= '1';
|
state <= REQUEST_CLASS;
|
state <= REQUEST_CLASS;
|
elsif (writeReady = '1') then
|
elsif (writeReady = '1') then
|
cyc_o <= '1';
|
|
stb_o <= '1';
|
|
we_o <= '1';
|
|
adr <= writeAddress;
|
adr <= writeAddress;
|
sel_o <= writeSelect;
|
|
datOut <= writePayload;
|
|
|
|
payloadUpdate <= '1';
|
payloadUpdate <= '1';
|
payloadIndex <= (others=>'0');
|
payloadIndex <= (others=>'0');
|
|
|
responsePayloadPresent <= '0';
|
responsePayloadPresent <= '0';
|
| Line 401... |
Line 445... |
|
|
when WRITE_CLASS =>
|
when WRITE_CLASS =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (ack_i = '1') then
|
state <= WRITE_CLASS_ACCESS;
|
|
|
|
when WRITE_CLASS_ACCESS =>
|
|
---------------------------------------------------------------------
|
|
--
|
|
---------------------------------------------------------------------
|
|
cyc_o <= '1';
|
|
stb_o <= '1';
|
|
we_o <= '1';
|
|
sel_o <= writeSelect;
|
|
datOut <= writePayload;
|
payloadUpdate <= '1';
|
payloadUpdate <= '1';
|
|
|
|
state <= WRITE_CLASS_ACK;
|
|
|
|
when WRITE_CLASS_ACK =>
|
|
---------------------------------------------------------------------
|
|
--
|
|
---------------------------------------------------------------------
|
|
if (ack_i = '1') then
|
adr <= std_logic_vector(unsigned(adr) + 1);
|
adr <= std_logic_vector(unsigned(adr) + 1);
|
|
|
if (payloadIndex /= writeLength) then
|
if (unsigned(payloadIndex) /= (unsigned(writeLength)+2)) then
|
datOut <= writePayload;
|
stb_o <= '0';
|
|
state <= WRITE_CLASS_ACCESS;
|
else
|
else
|
writeDone <= '1';
|
writeDone <= '1';
|
cyc_o <= '0';
|
cyc_o <= '0';
|
stb_o <= '0';
|
stb_o <= '0';
|
state <= WRITE_CLASS_RESPONSE;
|
state <= WRITE_CLASS_RESPONSE;
|
| Line 420... |
Line 482... |
|
|
when WRITE_CLASS_RESPONSE =>
|
when WRITE_CLASS_RESPONSE =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (writeDone = '1') then
|
if (responseDone = '1') or (writeResponse = '0') then
|
responseReady <= '0';
|
responseReady <= '0';
|
state <= IDLE;
|
state <= IDLE;
|
else
|
else
|
responseReady <= '1';
|
responseReady <= '1';
|
end if;
|
end if;
|
| Line 435... |
Line 497... |
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
--
|
-- Packet handlers.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
RequestClassInboundInst: RequestClassInbound
|
RequestClassInboundInst: RequestClassInbound
|
generic map(
|
generic map(
|
EXTENDED_ADDRESS=>EXTENDED_ADDRESS)
|
EXTENDED_ADDRESS=>EXTENDED_ADDRESS)
|
| Line 457... |
Line 519... |
tid_o=>requestTid,
|
tid_o=>requestTid,
|
address_o=>requestAddress,
|
address_o=>requestAddress,
|
length_o=>requestLength,
|
length_o=>requestLength,
|
select_o=>requestSelect,
|
select_o=>requestSelect,
|
done_i=>requestDone,
|
done_i=>requestDone,
|
slaveCyc_i=>inboundCyc,
|
inboundCyc_i=>inboundCyc,
|
slaveStb_i=>inboundStb,
|
inboundStb_i=>inboundStb,
|
slaveAdr_i=>inboundAdr,
|
inboundAdr_i=>inboundAdr,
|
slaveDat_i=>inboundDat,
|
inboundDat_i=>inboundDat,
|
slaveAck_o=>requestAck);
|
inboundAck_o=>requestAck);
|
|
|
WriteClassInboundInst: WriteClassInbound
|
WriteClassInboundInst: WriteClassInbound
|
generic map(
|
generic map(
|
EXTENDED_ADDRESS=>EXTENDED_ADDRESS)
|
EXTENDED_ADDRESS=>EXTENDED_ADDRESS)
|
port map(
|
port map(
|
clk=>clk,
|
clk=>clk,
|
areset_n=>areset_n,
|
areset_n=>areset_n,
|
enable=>enable,
|
enable=>enable,
|
ready_o=>writeReady,
|
ready_o=>writeReady,
|
|
responseNeeded_o=>writeResponse,
|
vc_o=>writeVc,
|
vc_o=>writeVc,
|
crf_o=>writeCrf,
|
crf_o=>writeCrf,
|
prio_o=>writePrio,
|
prio_o=>writePrio,
|
tt_o=>writeTt,
|
tt_o=>writeTt,
|
dstId_o=>writeDstId,
|
dstId_o=>writeDstId,
|
| Line 485... |
Line 548... |
select_o=>writeSelect,
|
select_o=>writeSelect,
|
payloadRead_i=>payloadUpdate,
|
payloadRead_i=>payloadUpdate,
|
payloadIndex_i=>payloadIndex,
|
payloadIndex_i=>payloadIndex,
|
payload_o=>writePayload,
|
payload_o=>writePayload,
|
done_i=>writeDone,
|
done_i=>writeDone,
|
slaveCyc_i=>inboundCyc,
|
inboundCyc_i=>inboundCyc,
|
slaveStb_i=>inboundStb,
|
inboundStb_i=>inboundStb,
|
slaveAdr_i=>inboundAdr,
|
inboundAdr_i=>inboundAdr,
|
slaveDat_i=>inboundDat,
|
inboundDat_i=>inboundDat,
|
slaveAck_o=>writeAck);
|
inboundAck_o=>writeAck);
|
|
|
ResponseClassOutboundInst: ResponseClassOutbound
|
ResponseClassOutboundInst: ResponseClassOutbound
|
port map(
|
port map(
|
clk=>clk,
|
clk=>clk,
|
areset_n=>areset_n,
|
areset_n=>areset_n,
|
| Line 511... |
Line 574... |
payloadLength_i=>requestLength,
|
payloadLength_i=>requestLength,
|
payloadWrite_i=>payloadUpdate,
|
payloadWrite_i=>payloadUpdate,
|
payloadIndex_i=>payloadIndex,
|
payloadIndex_i=>payloadIndex,
|
payload_i=>responsePayload,
|
payload_i=>responsePayload,
|
done_o=>responseDone,
|
done_o=>responseDone,
|
masterCyc_o=>outboundCyc,
|
outboundCyc_o=>outboundCyc(0),
|
masterStb_o=>outboundStb,
|
outboundStb_o=>outboundStb(0),
|
masterDat_o=>outboundDat,
|
outboundDat_o=>outboundDat(31 downto 0),
|
masterAck_i=>outboundAck);
|
outboundAck_i=>outboundAck(0));
|
|
|
|
-- Maintenance packet processing.
|
|
MaintenanceInst: RioLogicalMaintenance
|
|
port map(
|
|
clk=>clk,
|
|
areset_n=>areset_n,
|
|
enable=>enable,
|
|
configStb_o=>configStb,
|
|
configWe_o=>configWe,
|
|
configAdr_o=>configAdr,
|
|
configDat_o=>configDatWrite,
|
|
configDat_i=>configDatRead,
|
|
configAck_i=>configAck,
|
|
inboundCyc_i=>inboundCyc,
|
|
inboundStb_i=>inboundStb,
|
|
inboundAdr_i=>inboundAdr,
|
|
inboundDat_i=>inboundDat,
|
|
inboundAck_o=>maintenanceAck,
|
|
outboundCyc_o=>outboundCyc(1),
|
|
outboundStb_o=>outboundStb(1),
|
|
outboundDat_o=>outboundDat(63 downto 32),
|
|
outboundAck_i=>outboundAck(1));
|
|
|
|
-----------------------------------------------------------------------------
|
|
-- Common interface toward the packet queues.
|
|
-----------------------------------------------------------------------------
|
|
|
inboundAck <= requestAck or writeAck;
|
inboundAck <= requestAck or writeAck or maintenanceAck;
|
RioLogicalCommonInst: RioLogicalCommon
|
RioLogicalCommonInst: RioLogicalCommon
|
|
generic map(PORTS=>PORTS)
|
port map(
|
port map(
|
clk=>clk,
|
clk=>clk,
|
areset_n=>areset_n,
|
areset_n=>areset_n,
|
enable=>enable,
|
enable=>enable,
|
readFrameEmpty_i=>readFrameEmpty_i,
|
readFrameEmpty_i=>readFrameEmpty_i,
|
| Line 532... |
Line 622... |
writeFrameFull_i=>writeFrameFull_i,
|
writeFrameFull_i=>writeFrameFull_i,
|
writeFrame_o=>writeFrame_o,
|
writeFrame_o=>writeFrame_o,
|
writeFrameAbort_o=>writeFrameAbort_o,
|
writeFrameAbort_o=>writeFrameAbort_o,
|
writeContent_o=>writeContent_o,
|
writeContent_o=>writeContent_o,
|
writeContentData_o=>writeContentData_o,
|
writeContentData_o=>writeContentData_o,
|
masterCyc_o=>inboundCyc,
|
inboundCyc_o=>inboundCyc,
|
masterStb_o=>inboundStb,
|
inboundStb_o=>inboundStb,
|
masterAdr_o=>inboundAdr,
|
inboundAdr_o=>inboundAdr,
|
masterDat_o=>inboundDat,
|
inboundDat_o=>inboundDat,
|
masterAck_i=>inboundAck,
|
inboundAck_i=>inboundAck,
|
slaveCyc_i=>outboundCyc,
|
outboundCyc_i=>outboundCyc,
|
slaveStb_i=>outboundStb,
|
outboundStb_i=>outboundStb,
|
slaveDat_i=>outboundDat,
|
outboundDat_i=>outboundDat,
|
slaveAck_o=>outboundAck);
|
outboundAck_o=>outboundAck);
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Configuration memory.
|
-- Configuration memory.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- memoryConfig : process(clk, areset_n)
|
configAdrByte <= configAdr & "00";
|
-- begin
|
memoryConfig : process(clk, areset_n)
|
-- if (areset_n = '0') then
|
variable componentTag : std_logic_vector(31 downto 0);
|
-- configDataRead <= (others => '0');
|
variable hostBaseDeviceIdLocked : std_logic;
|
-- baseDeviceId <= DEFAULT_BASE_DEVICE_ID;
|
variable hostBaseDeviceId : std_logic_vector(15 downto 0);
|
-- componentTag <= (others => '0');
|
begin
|
-- hostBaseDeviceIdLocked <= '0';
|
if (areset_n = '0') then
|
-- hostBaseDeviceId <= (others => '1');
|
componentTag := (others => '0');
|
-- elsif (clk'event and clk = '1') then
|
hostBaseDeviceIdLocked := '0';
|
|
hostBaseDeviceId := (others => '1');
|
-- if (configEnable = '1') then
|
|
-- case (configAddress) is
|
configDatRead <= (others => '0');
|
-- when x"000000" =>
|
configAck <= '0';
|
-- -- Device Identity CAR. Read-only.
|
elsif (clk'event and clk = '1') then
|
-- configDataRead(31 downto 16) <= DEVICE_IDENTITY;
|
if (configAck = '0') then
|
-- configDataRead(15 downto 0) <= DEVICE_VENDOR_IDENTITY;
|
if (configStb = '1') then
|
-- when x"000004" =>
|
configAck <= '1';
|
-- -- Device Information CAR. Read-only.
|
configDatRead <= (others=>'0');
|
-- configDataRead(31 downto 0) <= DEVICE_REV;
|
|
-- when x"000008" =>
|
-- Check the address the access is for.
|
-- -- Assembly Identity CAR. Read-only.
|
case (configAdrByte) is
|
-- configDataRead(31 downto 16) <= ASSY_IDENTITY;
|
when x"000000" =>
|
-- configDataRead(15 downto 0) <= ASSY_VENDOR_IDENTITY;
|
-----------------------------------------------------------------
|
-- when x"00000c" =>
|
-- Device Identity CAR. Read-only.
|
-- -- Assembly Informaiton CAR. Read-only.
|
-----------------------------------------------------------------
|
-- -- Extended features pointer to "0000".
|
configDatRead(31 downto 16) <= DEVICE_IDENTITY;
|
-- configDataRead(31 downto 16) <= ASSY_REV;
|
configDatRead(15 downto 0) <= DEVICE_VENDOR_IDENTITY;
|
-- configDataRead(15 downto 0) <= x"0000";
|
|
-- when x"000010" =>
|
when x"000004" =>
|
-- -- Processing Element Features CAR. Read-only.
|
-----------------------------------------------------------------
|
-- -- Bridge(31), Memory(30), Processor(29), Switch(28).
|
-- Device Information CAR. Read-only.
|
-- configDataRead(31) <= '1';
|
-----------------------------------------------------------------
|
-- configDataRead(30 downto 4) <= (others => '0');
|
configDatRead(31 downto 0) <= DEVICE_REV;
|
-- configDataRead(3) <= '1'; -- support 16 bits common transport large system
|
|
-- configDataRead(2 downto 0) <= "001"; -- support 34 bits address
|
when x"000008" =>
|
-- when x"000018" =>
|
-----------------------------------------------------------------
|
-- -- Source Operations CAR. Read-only.
|
-- Assembly Identity CAR. Read-only.
|
-- configDataRead(31 downto 0) <= (others => '0');
|
-----------------------------------------------------------------
|
-- when x"00001C" =>
|
configDatRead(31 downto 16) <= ASSY_IDENTITY;
|
-- -- Destination Operations CAR. Read-only.
|
configDatRead(15 downto 0) <= ASSY_VENDOR_IDENTITY;
|
-- configDataRead(31 downto 16) <= (others => '0');
|
|
-- configDataRead(15) <= '1';
|
when x"00000c" =>
|
-- configDataRead(14) <= '1';
|
-----------------------------------------------------------------
|
-- configDataRead(13 downto 0) <= (others => '0');
|
-- Assembly Information CAR. Read-only.
|
-- when x"00004C" =>
|
-----------------------------------------------------------------
|
-- -- Processing Element Logical Layer Control CSR.
|
configDatRead(31 downto 16) <= ASSY_REV;
|
-- configDataRead(31 downto 3) <= (others => '0');
|
|
-- configDataRead(2 downto 0) <= "001"; -- support 34 bits address
|
when x"000010" =>
|
-- when x"000060" =>
|
-----------------------------------------------------------------
|
-- -- Base Device ID CSR.
|
-- Processing Element Features CAR. Read-only.
|
-- -- Only valid for end point devices.
|
-----------------------------------------------------------------
|
-- if (configWrite = '1') then
|
-- Bridge.
|
-- baseDeviceId <= configDataWrite(15 downto 0);
|
configDatRead(31) <= '1';
|
-- else
|
-- Extended addressing support, 34-bit addresses.
|
-- configDataRead(15 downto 0) <= baseDeviceId;
|
configDatRead(2 downto 0) <= "001";
|
-- end if;
|
|
-- when x"000068" =>
|
when x"000018" =>
|
-- -- Host Base Device ID Lock CSR.
|
-----------------------------------------------------------------
|
-- if (configWrite = '1') then
|
-- Source Operations CAR. Read-only.
|
-- -- Check if this field has been written before.
|
-----------------------------------------------------------------
|
-- if (hostBaseDeviceIdLocked = '0') then
|
-- Cannot act as a source of any packets.
|
-- -- The field has not been written.
|
|
-- -- Lock the field and set the host base device id.
|
when x"00001c" =>
|
-- hostBaseDeviceIdLocked <= '1';
|
-----------------------------------------------------------------
|
-- hostBaseDeviceId <= configDataWrite(15 downto 0);
|
-- Destination Operations CAR. Read-only.
|
-- else
|
-----------------------------------------------------------------
|
-- -- The field has been written.
|
-- Read, supported.
|
-- -- Check if the written data is the same as the stored.
|
configDatRead(15) <= '1';
|
-- if (hostBaseDeviceId = configDataWrite(15 downto 0)) then
|
-- Write, supported.
|
-- -- Same as stored, reset the value to its initial value.
|
configDatRead(14) <= '1';
|
-- hostBaseDeviceIdLocked <= '0';
|
-- Write-with-response, supported.
|
-- hostBaseDeviceId <= (others => '1');
|
configDatRead(12) <= '1';
|
-- else
|
|
-- -- Not writing the same as the stored value.
|
when x"00004c" =>
|
-- -- Ignore the write.
|
-----------------------------------------------------------------
|
-- end if;
|
-- Processing Element Logical Layer Control CSR.
|
-- end if;
|
-----------------------------------------------------------------
|
-- else
|
-- Extended addressing control, PE supports 34 bits addresses.
|
-- configDataRead(31 downto 16) <= (others => '0');
|
configDatRead(2 downto 0) <= "001";
|
-- configDataRead(15 downto 0) <= hostBaseDeviceId;
|
|
-- end if;
|
when x"000060" =>
|
-- when x"00006C" =>
|
-----------------------------------------------------------------
|
-- -- Component TAG CSR.
|
-- Base Device ID CSR.
|
-- if (configWrite = '1') then
|
-----------------------------------------------------------------
|
-- componentTag <= configDataWrite;
|
-- This is not used since this endpoint only replies to packets
|
-- else
|
-- and it can then use the destination deviceId as a source.
|
-- configDataRead <= componentTag;
|
|
-- end if;
|
when x"000068" =>
|
|
-----------------------------------------------------------------
|
-- when others =>
|
-- Host Base Device ID Lock CSR.
|
-- configDataRead <= (others => '0');
|
-----------------------------------------------------------------
|
-- end case;
|
|
-- else
|
-- Check if writing.
|
-- -- Config memory not enabled.
|
if (configWe = '1') then
|
-- end if;
|
-- Write access.
|
-- end if;
|
|
-- end process;
|
-- Check if this field has been written before.
|
|
if (hostBaseDeviceIdLocked = '0') then
|
|
-- The field has not been written.
|
|
-- Lock the field and set the host base device id.
|
|
hostBaseDeviceIdLocked := '1';
|
|
hostBaseDeviceId := configDatWrite(15 downto 0);
|
|
else
|
|
-- The field has been written.
|
|
-- Check if the written data is the same as the stored.
|
|
if (hostBaseDeviceId = configDatWrite(15 downto 0)) then
|
|
-- Same as stored, reset the value to its initial value.
|
|
hostBaseDeviceIdLocked := '0';
|
|
hostBaseDeviceId := (others => '1');
|
|
else
|
|
-- Not writing the same as the stored value.
|
|
-- Ignore the write.
|
|
end if;
|
|
end if;
|
|
end if;
|
|
|
|
configDatRead(15 downto 0) <= hostBaseDeviceId;
|
|
|
|
when x"00006C" =>
|
|
-----------------------------------------------------------------
|
|
-- Component TAG CSR.
|
|
-----------------------------------------------------------------
|
|
if (configWe = '1') then
|
|
componentTag := configDatWrite;
|
|
end if;
|
|
|
|
configDatRead <= componentTag;
|
|
|
|
when others =>
|
|
-----------------------------------------------------------------
|
|
-- Other access.
|
|
-----------------------------------------------------------------
|
|
-- Respond with all zeros.
|
|
configDatRead <= (others => '0');
|
|
end case;
|
|
end if;
|
|
else
|
|
configAck <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
end architecture;
|
end architecture;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
| Line 680... |
Line 814... |
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
|
length_o : out std_logic_vector(4 downto 0);
|
length_o : out std_logic_vector(4 downto 0);
|
select_o : out std_logic_vector(7 downto 0);
|
select_o : out std_logic_vector(7 downto 0);
|
done_i : in std_logic;
|
done_i : in std_logic;
|
|
|
slaveCyc_i : in std_logic;
|
inboundCyc_i : in std_logic;
|
slaveStb_i : in std_logic;
|
inboundStb_i : in std_logic;
|
slaveAdr_i : in std_logic_vector(7 downto 0);
|
inboundAdr_i : in std_logic_vector(7 downto 0);
|
slaveDat_i : in std_logic_vector(31 downto 0);
|
inboundDat_i : in std_logic_vector(31 downto 0);
|
slaveAck_o : out std_logic);
|
inboundAck_o : out std_logic);
|
end entity;
|
end entity;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
| Line 698... |
Line 832... |
signal state : StateType;
|
signal state : StateType;
|
|
|
signal rdsize : std_logic_vector(3 downto 0);
|
signal rdsize : std_logic_vector(3 downto 0);
|
signal wdptr : std_logic;
|
signal wdptr : std_logic;
|
|
|
signal slaveAck : std_logic;
|
signal inboundAck : std_logic;
|
signal complete : std_logic;
|
signal complete : std_logic;
|
|
|
signal packetIndex : natural range 0 to 68;
|
signal packetIndex : natural range 0 to 69;
|
|
|
begin
|
begin
|
|
|
slaveAck_o <= slaveAck;
|
inboundAck_o <= inboundAck;
|
|
|
ready_o <= complete when (state = READY) else '0';
|
ready_o <= complete when (state = READY) else '0';
|
|
|
RequestClass: process(clk, areset_n)
|
RequestClass: process(clk, areset_n)
|
begin
|
begin
|
| Line 717... |
Line 851... |
state <= RECEIVE_PACKET;
|
state <= RECEIVE_PACKET;
|
|
|
rdsize <= (others=>'0');
|
rdsize <= (others=>'0');
|
wdptr <= '0';
|
wdptr <= '0';
|
|
|
slaveAck <= '0';
|
inboundAck <= '0';
|
complete <= '0';
|
complete <= '0';
|
|
|
packetIndex <= 0;
|
packetIndex <= 0;
|
|
|
vc_o <= '0';
|
vc_o <= '0';
|
| Line 737... |
Line 871... |
when RECEIVE_PACKET =>
|
when RECEIVE_PACKET =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- This state waits for a new REQUEST class packet, receives it
|
-- This state waits for a new REQUEST class packet, receives it
|
-- and parses it.
|
-- and parses it.
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (slaveCyc_i = '1') then
|
if (inboundCyc_i = '1') then
|
if (slaveAck = '0') then
|
if (inboundAck = '0') then
|
if (slaveStb_i = '1') then
|
if (inboundStb_i = '1') then
|
if (slaveAdr_i = x"24") then
|
if (inboundAdr_i = x"24") then
|
-------------------------------------------------------------
|
-------------------------------------------------------------
|
-- NREAD packet parser.
|
-- NREAD packet parser.
|
-------------------------------------------------------------
|
-------------------------------------------------------------
|
case (packetIndex) is
|
case (packetIndex) is
|
when 0 =>
|
when 0 =>
|
-- x"0000" & ackid & vc & crf & prio & tt & ftype
|
-- x"0000" & ackid & vc & crf & prio & tt & ftype
|
vc_o <= slaveDat_i(9);
|
vc_o <= inboundDat_i(9);
|
crf_o <= slaveDat_i(8);
|
crf_o <= inboundDat_i(8);
|
prio_o <= slaveDat_i(7 downto 6);
|
prio_o <= inboundDat_i(7 downto 6);
|
tt_o <= slaveDat_i(5 downto 4);
|
tt_o <= inboundDat_i(5 downto 4);
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 1 =>
|
when 1 =>
|
-- dstid
|
-- dstid
|
dstId_o <= slaveDat_i;
|
dstId_o <= inboundDat_i;
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 2 =>
|
when 2 =>
|
-- srcid
|
-- srcid
|
srcId_o <= slaveDat_i;
|
srcId_o <= inboundDat_i;
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 3 =>
|
when 3 =>
|
-- transaction(3:0) & rdsize(3:0) & srcTID(7:0) & address(28:13)
|
-- transaction(3:0) & rdsize(3:0) & srcTID(7:0) & address(28:13)
|
-- REMARK: Add support for extended addresses here...
|
rdsize <= inboundDat_i(27 downto 24);
|
rdsize <= slaveDat_i(27 downto 24);
|
tid_o <= inboundDat_i(23 downto 16);
|
tid_o <= slaveDat_i(23 downto 16);
|
address_o(28 downto 13) <= inboundDat_i(15 downto 0);
|
address_o(28 downto 13) <= slaveDat_i(15 downto 0);
|
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 4 =>
|
when 4 =>
|
-- address(12:0) & wdptr & xamsbs(1:0) & crc(15:0)
|
-- address(12:0) & wdptr & xamsbs(1:0) & crc(15:0)
|
address_o(12 downto 0) <= slaveDat_i(31 downto 19);
|
address_o(12 downto 0) <= inboundDat_i(31 downto 19);
|
wdptr <= slaveDat_i(18);
|
wdptr <= inboundDat_i(18);
|
address_o(30 downto 29) <= slaveDat_i(17 downto 16);
|
address_o(30 downto 29) <= inboundDat_i(17 downto 16);
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
complete <= '1';
|
complete <= '1';
|
when others =>
|
when others =>
|
-- There should be no more content in an NREAD.
|
-- There should be no more content in an NREAD.
|
-- Discard.
|
-- Discard.
|
end case;
|
end case;
|
slaveAck <= '1';
|
inboundAck <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
else
|
else
|
slaveAck <= '0';
|
inboundAck <= '0';
|
end if;
|
end if;
|
else
|
else
|
if (complete = '1') then
|
if (complete = '1') then
|
state <= READY;
|
state <= READY;
|
end if;
|
end if;
|
| Line 934... |
Line 1067... |
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- REMARK: Support inbound data with full bandwidth, not just half...
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
use work.rio_common.all;
|
use work.rio_common.all;
|
|
|
| Line 953... |
Line 1085... |
clk : in std_logic;
|
clk : in std_logic;
|
areset_n : in std_logic;
|
areset_n : in std_logic;
|
enable : in std_logic;
|
enable : in std_logic;
|
|
|
ready_o : out std_logic;
|
ready_o : out std_logic;
|
|
responseNeeded_o : out std_logic;
|
vc_o : out std_logic;
|
vc_o : out std_logic;
|
crf_o : out std_logic;
|
crf_o : out std_logic;
|
prio_o : out std_logic_vector(1 downto 0);
|
prio_o : out std_logic_vector(1 downto 0);
|
tt_o : out std_logic_vector(1 downto 0);
|
tt_o : out std_logic_vector(1 downto 0);
|
dstId_o : out std_logic_vector(31 downto 0);
|
dstId_o : out std_logic_vector(31 downto 0);
|
| Line 968... |
Line 1101... |
payloadRead_i : in std_logic;
|
payloadRead_i : in std_logic;
|
payloadIndex_i : in std_logic_vector(4 downto 0);
|
payloadIndex_i : in std_logic_vector(4 downto 0);
|
payload_o : out std_logic_vector(63 downto 0);
|
payload_o : out std_logic_vector(63 downto 0);
|
done_i : in std_logic;
|
done_i : in std_logic;
|
|
|
slaveCyc_i : in std_logic;
|
inboundCyc_i : in std_logic;
|
slaveStb_i : in std_logic;
|
inboundStb_i : in std_logic;
|
slaveAdr_i : in std_logic_vector(7 downto 0);
|
inboundAdr_i : in std_logic_vector(7 downto 0);
|
slaveDat_i : in std_logic_vector(31 downto 0);
|
inboundDat_i : in std_logic_vector(31 downto 0);
|
slaveAck_o : out std_logic);
|
inboundAck_o : out std_logic);
|
end entity;
|
end entity;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
| Line 1002... |
Line 1135... |
signal state : StateType;
|
signal state : StateType;
|
|
|
signal wdptr : std_logic;
|
signal wdptr : std_logic;
|
signal wrsize : std_logic_vector(3 downto 0);
|
signal wrsize : std_logic_vector(3 downto 0);
|
|
|
signal slaveAck : std_logic;
|
signal inboundAck : std_logic;
|
signal complete : std_logic;
|
signal complete : std_logic;
|
|
|
signal packetIndex : natural range 0 to 68;
|
signal packetIndex : natural range 0 to 69;
|
|
|
signal doubleWord : std_logic_vector(63 downto 16);
|
signal doubleWord : std_logic_vector(63 downto 16);
|
|
|
signal memoryWrite : std_logic;
|
signal memoryWrite : std_logic;
|
signal memoryAddress : std_logic_vector(4 downto 0);
|
signal memoryAddress : std_logic_vector(4 downto 0);
|
signal memoryDataIn : std_logic_vector(63 downto 0);
|
signal memoryDataIn : std_logic_vector(63 downto 0);
|
|
|
|
|
begin
|
begin
|
|
|
slaveAck_o <= slaveAck;
|
inboundAck_o <= inboundAck;
|
|
|
ready_o <= complete when (state = READY) else '0';
|
ready_o <= complete when (state = READY) else '0';
|
|
|
WriteClass: process(clk, areset_n)
|
WriteClass: process(clk, areset_n)
|
begin
|
begin
|
| Line 1028... |
Line 1161... |
state <= RECEIVE_PACKET;
|
state <= RECEIVE_PACKET;
|
|
|
wdptr <= '0';
|
wdptr <= '0';
|
wrsize <= (others=>'0');
|
wrsize <= (others=>'0');
|
|
|
slaveAck <= '0';
|
inboundAck <= '0';
|
complete <= '0';
|
complete <= '0';
|
|
responseNeeded_o <= '0';
|
|
|
packetIndex <= 0;
|
packetIndex <= 0;
|
doubleWord <= (others=>'0');
|
doubleWord <= (others=>'0');
|
|
|
memoryWrite <= '0';
|
memoryWrite <= '0';
|
| Line 1049... |
Line 1183... |
tid_o <= (others=>'0');
|
tid_o <= (others=>'0');
|
address_o <= (others=>'0');
|
address_o <= (others=>'0');
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
case state is
|
case state is
|
when RECEIVE_PACKET =>
|
when RECEIVE_PACKET =>
|
---------------------------------------------------------------------
|
if (inboundCyc_i = '1') then
|
-- This state waits for a new WRITE class packet, receives it
|
if (inboundAck = '0') then
|
-- and parses it.
|
if (inboundStb_i = '1') then
|
---------------------------------------------------------------------
|
if ((inboundAdr_i = x"55") or (inboundAdr_i = x"54")) then
|
if (slaveCyc_i = '1') then
|
|
if (slaveAck = '0') then
|
|
if (slaveStb_i = '1') then
|
|
if (slaveAdr_i = x"55") then
|
|
-------------------------------------------------------------
|
-------------------------------------------------------------
|
-- NWRITER packet parser.
|
-- NWRITE/NWRITER packet parser.
|
-------------------------------------------------------------
|
-------------------------------------------------------------
|
-- REMARK: Add support for NWRITE without response...
|
|
case (packetIndex) is
|
case (packetIndex) is
|
when 0 =>
|
when 0 =>
|
-- x"0000" & ackid & vc & crf & prio & tt & ftype
|
-- x"0000" & ackid & vc & crf & prio & tt & ftype
|
vc_o <= slaveDat_i(9);
|
vc_o <= inboundDat_i(9);
|
crf_o <= slaveDat_i(8);
|
crf_o <= inboundDat_i(8);
|
prio_o <= slaveDat_i(7 downto 6);
|
prio_o <= inboundDat_i(7 downto 6);
|
tt_o <= slaveDat_i(5 downto 4);
|
tt_o <= inboundDat_i(5 downto 4);
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 1 =>
|
when 1 =>
|
-- destId
|
-- destId
|
dstId_o <= slaveDat_i;
|
dstId_o <= inboundDat_i;
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 2 =>
|
when 2 =>
|
-- srcId
|
-- srcId
|
srcId_o <= slaveDat_i;
|
srcId_o <= inboundDat_i;
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 3 =>
|
when 3 =>
|
-- transaction & wrsize & srcTID & address(28:13)
|
-- transaction & wrsize & srcTID & address(28:13)
|
-- REMARK: Add support for extended addresses here...
|
-- REMARK: Add support for extended addresses here...
|
wrsize <= slaveDat_i(27 downto 24);
|
if (inboundDat_i(31 downto 28) = "0101") then
|
tid_o <= slaveDat_i(23 downto 16);
|
responseNeeded_o <= '1';
|
address_o(28 downto 13) <= slaveDat_i(15 downto 0);
|
else
|
|
responseNeeded_o <= '0';
|
|
end if;
|
|
wrsize <= inboundDat_i(27 downto 24);
|
|
tid_o <= inboundDat_i(23 downto 16);
|
|
address_o(28 downto 13) <= inboundDat_i(15 downto 0);
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 4 =>
|
when 4 =>
|
-- address(12:0) & wdptr & xamsbs(1:0) & double-word(63:48)
|
-- address(12:0) & wdptr & xamsbs(1:0) & double-word(63:48)
|
address_o(12 downto 0) <= slaveDat_i(31 downto 19);
|
address_o(12 downto 0) <= inboundDat_i(31 downto 19);
|
wdptr <= slaveDat_i(18);
|
wdptr <= inboundDat_i(18);
|
doubleWord(63 downto 48) <= slaveDat_i(15 downto 0);
|
address_o(30 downto 29) <= inboundDat_i(17 downto 16);
|
|
doubleWord(63 downto 48) <= inboundDat_i(15 downto 0);
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 | 33 | 35 |
|
when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 | 33 | 35 |
|
37 | 39 | 41 | 43 | 45 | 47 | 49 | 51 | 53 | 55 | 57 | 59 | 61 | 63 | 65 | 67 =>
|
37 | 39 | 41 | 43 | 45 | 47 | 49 | 51 | 53 | 55 | 57 | 59 | 61 | 63 | 65 | 67 =>
|
-- double-word(47:16)
|
-- double-word(47:16)
|
doubleWord(31 downto 16) <= slaveDat_i(15 downto 0);
|
doubleWord(47 downto 16) <= inboundDat_i;
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 32 | 34 |
|
when 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 32 | 34 |
|
36 | 38 | 40 | 42 | 44 | 46 | 48 | 50 | 52 | 54 | 56 | 58 | 60 | 62 | 64 | 66 =>
|
36 | 38 | 40 | 42 | 44 | 46 | 48 | 50 | 52 | 54 | 56 | 58 | 60 | 62 | 64 | 66 | 68 =>
|
-- double-word(15:0) & double-word(63:48)
|
-- double-word(15:0) & double-word(63:48)
|
doubleWord(63 downto 48) <= slaveDat_i(15 downto 0);
|
doubleWord(63 downto 48) <= inboundDat_i(15 downto 0);
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
|
|
memoryWrite <= '1';
|
memoryWrite <= '1';
|
memoryDataIn <= doubleWord(63 downto 16) & slaveDat_i(31 downto 16);
|
memoryDataIn <= doubleWord(63 downto 16) & inboundDat_i(31 downto 16);
|
complete <= '1';
|
|
when others =>
|
when others =>
|
-- There should be no more content in an NWRITE request.
|
-- There should be no more content in an NWRITE/NWRITER request.
|
-- Discard.
|
-- Discard.
|
end case;
|
end case;
|
slaveAck <= '1';
|
inboundAck <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
else
|
else
|
if (memoryWrite = '1') then
|
if (memoryWrite = '1') then
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
end if;
|
end if;
|
|
|
memoryWrite <= '0';
|
memoryWrite <= '0';
|
slaveAck <= '0';
|
inboundAck <= '0';
|
end if;
|
end if;
|
else
|
else
|
if (complete = '1') then
|
if (packetIndex >= 6) then
|
|
complete <= '1';
|
state <= READY;
|
state <= READY;
|
end if;
|
else
|
packetIndex <= 0;
|
packetIndex <= 0;
|
memoryAddress <= (others=>'0');
|
memoryAddress <= (others=>'0');
|
end if;
|
end if;
|
|
end if;
|
|
|
when READY =>
|
when READY =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- Wait for the handler of the packet to signal that it has been
|
-- Wait for the handler of the packet to signal that it has been
|
-- processed.
|
-- processed.
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (done_i = '1') then
|
if (done_i = '1') then
|
|
packetIndex <= 0;
|
|
memoryAddress <= (others=>'0');
|
complete <= '0';
|
complete <= '0';
|
state <= RECEIVE_PACKET;
|
state <= RECEIVE_PACKET;
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
| Line 1196... |
Line 1334... |
select_o <= "11111110";
|
select_o <= "11111110";
|
when "1011" =>
|
when "1011" =>
|
length_o <= "00000";
|
length_o <= "00000";
|
select_o <= "11111111";
|
select_o <= "11111111";
|
when others =>
|
when others =>
|
length_o <= memoryAddress;
|
length_o <= std_logic_vector(unsigned(memoryAddress)-1);
|
select_o <= "11111111";
|
select_o <= "11111111";
|
end case;
|
end case;
|
else
|
else
|
case wrsize is
|
case wrsize is
|
when "0000" =>
|
when "0000" =>
|
| Line 1235... |
Line 1373... |
select_o <= "00111111";
|
select_o <= "00111111";
|
when "1010" =>
|
when "1010" =>
|
length_o <= "00000";
|
length_o <= "00000";
|
select_o <= "01111111";
|
select_o <= "01111111";
|
when others =>
|
when others =>
|
length_o <= memoryAddress;
|
length_o <= std_logic_vector(unsigned(memoryAddress)-1);
|
select_o <= "11111111";
|
select_o <= "11111111";
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
| Line 1295... |
Line 1433... |
payloadWrite_i : in std_logic;
|
payloadWrite_i : in std_logic;
|
payloadIndex_i : in std_logic_vector(4 downto 0);
|
payloadIndex_i : in std_logic_vector(4 downto 0);
|
payload_i : in std_logic_vector(63 downto 0);
|
payload_i : in std_logic_vector(63 downto 0);
|
done_o : out std_logic;
|
done_o : out std_logic;
|
|
|
masterCyc_o : out std_logic;
|
outboundCyc_o : out std_logic;
|
masterStb_o : out std_logic;
|
outboundStb_o : out std_logic;
|
masterDat_o : out std_logic_vector(31 downto 0);
|
outboundDat_o : out std_logic_vector(31 downto 0);
|
masterAck_i : in std_logic);
|
outboundAck_i : in std_logic);
|
end entity;
|
end entity;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
| Line 1356... |
Line 1494... |
memoryEnable <= '0';
|
memoryEnable <= '0';
|
memoryAddress <= (others=>'0');
|
memoryAddress <= (others=>'0');
|
|
|
done_o <= '0';
|
done_o <= '0';
|
|
|
masterCyc_o <= '0';
|
outboundCyc_o <= '0';
|
masterStb_o <= '0';
|
outboundStb_o <= '0';
|
masterDat_o <= (others=>'0');
|
outboundDat_o <= (others=>'0');
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
if (enable = '1') then
|
if (enable = '1') then
|
case state is
|
case state is
|
when WAIT_PACKET =>
|
when WAIT_PACKET =>
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
--
|
--
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
if (ready_i = '1') then
|
if (ready_i = '1') then
|
masterCyc_o <= '1';
|
outboundCyc_o <= '1';
|
masterStb_o <= '1';
|
outboundStb_o <= '1';
|
masterDat_o <= header;
|
outboundDat_o <= header;
|
|
|
packetIndex <= 1;
|
packetIndex <= 1;
|
responsePayloadIndex <= (others=>'0');
|
responsePayloadIndex <= (others=>'0');
|
|
|
memoryEnable <= '1';
|
memoryEnable <= '1';
|
| Line 1384... |
Line 1522... |
|
|
when SEND_RESPONSE =>
|
when SEND_RESPONSE =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (masterAck_i = '1') then
|
if (outboundAck_i = '1') then
|
case (packetIndex) is
|
case (packetIndex) is
|
when 1 =>
|
when 1 =>
|
-- destination
|
-- destination
|
masterDat_o <= dstId_i;
|
outboundDat_o <= dstId_i;
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 2 =>
|
when 2 =>
|
-- source
|
-- source
|
masterDat_o <= srcId_i;
|
outboundDat_o <= srcId_i;
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 3 =>
|
when 3 =>
|
-- transaction & status & targetTID & double-word0(63:48)
|
-- transaction & status & targetTID & double-word0(63:48)
|
if (error_i = '0') then
|
if (error_i = '0') then
|
if (payloadPresent_i = '0') then
|
if (payloadPresent_i = '0') then
|
masterDat_o <= "0000" & "0000" & tid_i & x"0000";
|
outboundDat_o <= "0000" & "0000" & tid_i & x"0000";
|
state <= WAIT_COMPLETE;
|
state <= WAIT_COMPLETE;
|
else
|
else
|
masterDat_o <= "1000" & "0000" & tid_i & memoryDataRead(63 downto 48);
|
outboundDat_o <= "1000" & "0000" & tid_i & memoryDataRead(63 downto 48);
|
end if;
|
end if;
|
else
|
else
|
masterDat_o <= "0000" & "0111" & tid_i & x"0000";
|
outboundDat_o <= "0000" & "0111" & tid_i & x"0000";
|
state <= WAIT_COMPLETE;
|
state <= WAIT_COMPLETE;
|
end if;
|
end if;
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 4 | 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 32 | 34 |
|
when 4 | 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 32 | 34 |
|
36 | 38 | 40 | 42 | 44 | 46 | 48 | 50 | 52 | 54 | 56 | 58 | 60 | 62 | 64 | 66 =>
|
36 | 38 | 40 | 42 | 44 | 46 | 48 | 50 | 52 | 54 | 56 | 58 | 60 | 62 | 64 | 66 =>
|
-- double-wordN(47:16)
|
-- double-wordN(47:16)
|
masterDat_o <= memoryDataRead(47 downto 16);
|
outboundDat_o <= memoryDataRead(47 downto 16);
|
responsePayload <= memoryDataRead(15 downto 0);
|
responsePayload <= memoryDataRead(15 downto 0);
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 | 33 | 35 |
|
when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 | 33 | 35 |
|
37 | 39 | 41 | 43 | 45 | 47 | 49 | 51 | 53 | 55 | 57 | 59 | 61 | 63 | 65 | 67 =>
|
37 | 39 | 41 | 43 | 45 | 47 | 49 | 51 | 53 | 55 | 57 | 59 | 61 | 63 | 65 | 67 =>
|
-- double-wordN(15:0) & double-wordN(63:48)
|
-- double-wordN(15:0) & double-wordN(63:48)
|
masterDat_o <= responsePayload & memoryDataRead(63 downto 48);
|
outboundDat_o <= responsePayload & memoryDataRead(63 downto 48);
|
packetIndex <= packetIndex + 1;
|
packetIndex <= packetIndex + 1;
|
|
|
responsePayloadIndex <=
|
responsePayloadIndex <=
|
std_logic_vector(unsigned(responsePayloadIndex) + 1);
|
std_logic_vector(unsigned(responsePayloadIndex) + 1);
|
|
|
| Line 1439... |
Line 1577... |
|
|
when WAIT_COMPLETE =>
|
when WAIT_COMPLETE =>
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
--
|
--
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
if (masterAck_i = '1') then
|
if (outboundAck_i = '1') then
|
masterCyc_o <= '0';
|
outboundCyc_o <= '0';
|
masterStb_o <= '0';
|
outboundStb_o <= '0';
|
state <= RESPONSE_DONE;
|
state <= RESPONSE_DONE;
|
end if;
|
end if;
|
|
|
when RESPONSE_DONE =>
|
when RESPONSE_DONE =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
