| Line 262... |
Line 262... |
|
|
empty_o : out std_logic;
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empty_o : out std_logic;
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read_i : in std_logic;
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read_i : in std_logic;
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data_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
|
|
full_o : out std_logic;
|
|
write_i : in std_logic;
|
write_i : in std_logic;
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data_i : in std_logic_vector(DATA_WIDTH-1 downto 0));
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data_i : in std_logic_vector(DATA_WIDTH-1 downto 0));
|
end component;
|
end component;
|
|
|
component RioTransmitter is
|
component RioTransmitter is
|
| Line 434... |
Line 433... |
port map(
|
port map(
|
clk=>clk, areset_n=>areset_n,
|
clk=>clk, areset_n=>areset_n,
|
empty_o=>txControlReadEmpty(i),
|
empty_o=>txControlReadEmpty(i),
|
read_i=>txControlRead(i),
|
read_i=>txControlRead(i),
|
data_o=>txControlReadSymbol(12*(i+1) downto 12*i),
|
data_o=>txControlReadSymbol(12*(i+1) downto 12*i),
|
full_o=>open,
|
|
write_i=>txControlWrite(i),
|
write_i=>txControlWrite(i),
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data_i=>txControlWriteSymbol(12*(i+1) downto 12*i));
|
data_i=>txControlWriteSymbol(12*(i+1) downto 12*i));
|
|
|
RxSymbolFifo: RioFifo
|
RxSymbolFifo: RioFifo
|
generic map(DEPTH_WIDTH=>5, DATA_WIDTH=>13)
|
generic map(DEPTH_WIDTH=>5, DATA_WIDTH=>13)
|
port map(
|
port map(
|
clk=>clk, areset_n=>areset_n,
|
clk=>clk, areset_n=>areset_n,
|
empty_o=>rxControlReadEmpty(i),
|
empty_o=>rxControlReadEmpty(i),
|
read_i=>rxControlRead(i),
|
read_i=>rxControlRead(i),
|
data_o=>rxControlReadSymbol(12*(i+1) downto 12*i),
|
data_o=>rxControlReadSymbol(12*(i+1) downto 12*i),
|
full_o=>open,
|
|
write_i=>rxControlWrite(i),
|
write_i=>rxControlWrite(i),
|
data_i=>rxControlWriteSymbol(12*(i+1) downto 12*i));
|
data_i=>rxControlWriteSymbol(12*(i+1) downto 12*i));
|
end generate;
|
end generate;
|
|
|
inboundType <= inboundSymbol_i(2+(32*NUMBER_WORDS-1) downto 1+(32*NUMBER_WORDS-1));
|
inboundType <= inboundSymbol_i(2+(32*NUMBER_WORDS-1) downto 1+(32*NUMBER_WORDS-1));
|
| Line 1340... |
Line 1337... |
|
|
-- This process decide which stype1-part of a control symbols to send as well
|
-- This process decide which stype1-part of a control symbols to send as well
|
-- as all data symbols.
|
-- as all data symbols.
|
process(readWindowEmpty_i, bufferStatus_i,
|
process(readWindowEmpty_i, bufferStatus_i,
|
recoverActive_i, ackId_i, operational_i, outputErrorStopped_i, portEnable_i, readContentData_i, readContentWords_i, readContentEnd_i,
|
recoverActive_i, ackId_i, operational_i, outputErrorStopped_i, portEnable_i, readContentData_i, readContentWords_i, readContentEnd_i,
|
frameState_i, frameWordCounter_i, frameContent_i,
|
frameState_i, frameWordCounter_i, frameContent_i, maintenanceClass_i,
|
ackIdWindow_i,
|
ackIdWindow_i,
|
sendRestartFromRetry, sendLinkRequest,
|
sendRestartFromRetry, sendLinkRequest,
|
fatalError_i)
|
fatalError_i)
|
begin
|
begin
|
readFrameRestartOut <= '0';
|
readFrameRestartOut <= '0';
|
| Line 2904... |
Line 2901... |
|
|
empty_o : out std_logic;
|
empty_o : out std_logic;
|
read_i : in std_logic;
|
read_i : in std_logic;
|
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
|
|
full_o : out std_logic;
|
|
write_i : in std_logic;
|
write_i : in std_logic;
|
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0));
|
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0));
|
end entity;
|
end entity;
|
|
|
|
|
| Line 2937... |
Line 2933... |
|
|
signal readAddress : std_logic_vector(DEPTH_WIDTH-1 downto 0);
|
signal readAddress : std_logic_vector(DEPTH_WIDTH-1 downto 0);
|
signal readAddressInc : std_logic_vector(DEPTH_WIDTH-1 downto 0);
|
signal readAddressInc : std_logic_vector(DEPTH_WIDTH-1 downto 0);
|
signal writeAddress : std_logic_vector(DEPTH_WIDTH-1 downto 0);
|
signal writeAddress : std_logic_vector(DEPTH_WIDTH-1 downto 0);
|
signal writeAddressInc : std_logic_vector(DEPTH_WIDTH-1 downto 0);
|
signal writeAddressInc : std_logic_vector(DEPTH_WIDTH-1 downto 0);
|
|
|
signal change : std_logic;
|
|
begin
|
begin
|
|
|
-- REMARK: Remove full here...
|
|
empty_o <= empty;
|
empty_o <= empty;
|
full_o <= full;
|
|
|
|
readAddressInc <= std_logic_vector(unsigned(readAddress) + 1);
|
readAddressInc <= std_logic_vector(unsigned(readAddress) + 1);
|
writeAddressInc <= std_logic_vector(unsigned(writeAddress) + 1);
|
writeAddressInc <= std_logic_vector(unsigned(writeAddress) + 1);
|
|
|
process(areset_n, clk)
|
process(areset_n, clk)
|
