Subversion Repositories rio

-------------------------------------------------------------------------------

-- RioFifo1

-- Simple fifo which is one entry deep.

-------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

-------------------------------------------------------------------------------

-- Entity for RioFifo1.

-------------------------------------------------------------------------------

entity RioFifo1 is

  generic(

    WIDTH : natural);

  port(

    clk : in std_logic;

    areset_n : in std_logic;

    empty_o : out std_logic;

    read_i : in std_logic;

    data_o : out std_logic_vector(WIDTH-1 downto 0);

    full_o : out std_logic;

    write_i : in std_logic;

    data_i : in std_logic_vector(WIDTH-1 downto 0));

end entity;

-------------------------------------------------------------------------------

-- Architecture for RioFifo1.

-------------------------------------------------------------------------------

architecture RioFifo1Impl of RioFifo1 is

  signal empty : std_logic;

  signal full : std_logic;

begin

  empty_o <= empty;

  full_o <= full;

  process(areset_n, clk)

  begin

    if (areset_n = '0') then

      empty <= '1';

      full <= '0';

      data_o <= (others => '0');

    elsif (clk'event and clk = '1') then

      if (empty = '1') then

        if (write_i = '1') then

          empty <= '0';

          full <= '1';

          data_o <= data_i;

        end if;

      else

        if (read_i = '1') then

          empty <= '1';

          full <= '0';

        end if;

      end if;

    end if;

  end process;