OpenCores
URL https://opencores.org/ocsvn/rio/rio/trunk

Subversion Repositories rio

[/] [rio/] [trunk/] [rtl/] [vhdl/] [RioSwitch.vhd] - Diff between revs 2 and 28

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 2 Rev 28
Line 74... Line 74... 
    writeContent_o : out Array1(SWITCH_PORTS-1 downto 0);
 
    writeContent_o : out Array1(SWITCH_PORTS-1 downto 0);
 
    writeContentData_o : out Array32(SWITCH_PORTS-1 downto 0);
 
    writeContentData_o : out Array32(SWITCH_PORTS-1 downto 0);
 
 
 
 
 
    readFrameEmpty_i : in Array1(SWITCH_PORTS-1 downto 0);
 
    readFrameEmpty_i : in Array1(SWITCH_PORTS-1 downto 0);
 
    readFrame_o : out Array1(SWITCH_PORTS-1 downto 0);
 
    readFrame_o : out Array1(SWITCH_PORTS-1 downto 0);
 
    readFrameRestart_o : out Array1(SWITCH_PORTS-1 downto 0);
 
 
 
    readFrameAborted_i : in Array1(SWITCH_PORTS-1 downto 0);
 
 
 
    readContentEmpty_i : in Array1(SWITCH_PORTS-1 downto 0);
 
 
 
    readContent_o : out Array1(SWITCH_PORTS-1 downto 0);
 
    readContent_o : out Array1(SWITCH_PORTS-1 downto 0);
 
    readContentEnd_i : in Array1(SWITCH_PORTS-1 downto 0);
 
    readContentEnd_i : in Array1(SWITCH_PORTS-1 downto 0);
 
    readContentData_i : in Array32(SWITCH_PORTS-1 downto 0);
 
    readContentData_i : in Array32(SWITCH_PORTS-1 downto 0);
 
 
 
 
 
    portLinkTimeout_o : out std_logic_vector(23 downto 0);
 
    portLinkTimeout_o : out std_logic_vector(23 downto 0);
Line 241... Line 238... 
      lookupData_i : in std_logic_vector(7 downto 0);
 
      lookupData_i : in std_logic_vector(7 downto 0);
 
      lookupAck_i : in std_logic;
 
      lookupAck_i : in std_logic;
 
 
 
 
 
      readFrameEmpty_i : in std_logic;
 
      readFrameEmpty_i : in std_logic;
 
      readFrame_o : out std_logic;
 
      readFrame_o : out std_logic;
 
      readFrameRestart_o : out std_logic;
 
 
 
      readFrameAborted_i : in std_logic;
 
 
 
      readContentEmpty_i : in std_logic;
 
 
 
      readContent_o : out std_logic;
 
      readContent_o : out std_logic;
 
      readContentEnd_i : in std_logic;
 
      readContentEnd_i : in std_logic;
 
      readContentData_i : in std_logic_vector(31 downto 0);
 
      readContentData_i : in std_logic_vector(31 downto 0);
 
      writeFrameFull_i : in std_logic;
 
      writeFrameFull_i : in std_logic;
 
      writeFrame_o : out std_logic;
 
      writeFrame_o : out std_logic;
Line 329... Line 323... 
        slaveData_o=>slaveDataRead(portIndex), slaveAck_o=>slaveAck(portIndex),
 
        slaveData_o=>slaveDataRead(portIndex), slaveAck_o=>slaveAck(portIndex),
 
        lookupStb_o=>masterLookupStb(portIndex),
 
        lookupStb_o=>masterLookupStb(portIndex),
 
        lookupAddr_o=>masterLookupAddr(portIndex),
 
        lookupAddr_o=>masterLookupAddr(portIndex),
 
        lookupData_i=>masterLookupData(portIndex), lookupAck_i=>masterLookupAck(portIndex),
 
        lookupData_i=>masterLookupData(portIndex), lookupAck_i=>masterLookupAck(portIndex),
 
        readFrameEmpty_i=>readFrameEmpty_i(portIndex), readFrame_o=>readFrame_o(portIndex),
 
        readFrameEmpty_i=>readFrameEmpty_i(portIndex), readFrame_o=>readFrame_o(portIndex),
 
        readFrameRestart_o=>readFrameRestart_o(portIndex),
 
        readContent_o=>readContent_o(portIndex),
 
        readFrameAborted_i=>readFrameAborted_i(portIndex),
 
 
 
        readContentEmpty_i=>readContentEmpty_i(portIndex), readContent_o=>readContent_o(portIndex),
 
 
 
        readContentEnd_i=>readContentEnd_i(portIndex), readContentData_i=>readContentData_i(portIndex),
 
        readContentEnd_i=>readContentEnd_i(portIndex), readContentData_i=>readContentData_i(portIndex),
 
        writeFrameFull_i=>writeFrameFull_i(portIndex), writeFrame_o=>writeFrame_o(portIndex),
 
        writeFrameFull_i=>writeFrameFull_i(portIndex), writeFrame_o=>writeFrame_o(portIndex),
 
        writeFrameAbort_o=>writeFrameAbort_o(portIndex), writeContent_o=>writeContent_o(portIndex),
 
        writeFrameAbort_o=>writeFrameAbort_o(portIndex), writeContent_o=>writeContent_o(portIndex),
 
        writeContentData_o=>writeContentData_o(portIndex));
 
        writeContentData_o=>writeContentData_o(portIndex));
 
  end generate;
 
  end generate;
Line 428... Line 420... 
    lookupAck_i : in std_logic;
 
    lookupAck_i : in std_logic;
 
 
 
 
 
    -- Physical port frame buffer interface.
 
    -- Physical port frame buffer interface.
 
    readFrameEmpty_i : in std_logic;
 
    readFrameEmpty_i : in std_logic;
 
    readFrame_o : out std_logic;
 
    readFrame_o : out std_logic;
 
    readFrameRestart_o : out std_logic;
 
 
 
    readFrameAborted_i : in std_logic;
 
 
 
    readContentEmpty_i : in std_logic;
 
 
 
    readContent_o : out std_logic;
 
    readContent_o : out std_logic;
 
    readContentEnd_i : in std_logic;
 
    readContentEnd_i : in std_logic;
 
    readContentData_i : in std_logic_vector(31 downto 0);
 
    readContentData_i : in std_logic_vector(31 downto 0);
 
    writeFrameFull_i : in std_logic;
 
    writeFrameFull_i : in std_logic;
 
    writeFrame_o : out std_logic;
 
    writeFrame_o : out std_logic;
Line 448... Line 437... 
-- Architecture for SwitchPort.
 
-- Architecture for SwitchPort.
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
architecture SwitchPortImpl of SwitchPort is
 
architecture SwitchPortImpl of SwitchPort is
 
 
 
 
 
  type MasterStateType is (STATE_IDLE,
 
  type MasterStateType is (STATE_IDLE,
 
                           STATE_WAIT_HEADER_0, STATE_READ_HEADER_0,
 
                           STATE_ERROR,
 
 
 
                           STATE_WAIT_HEADER_0,
 
 
 
                           STATE_READ_HEADER_0,
 
                           STATE_READ_PORT_LOOKUP,
 
                           STATE_READ_PORT_LOOKUP,
 
                           STATE_READ_TARGET_PORT,
 
                           STATE_READ_TARGET_PORT,
 
                           STATE_WAIT_TARGET_PORT,
 
                           STATE_WAIT_TARGET_PORT,
 
                           STATE_WAIT_TARGET_WRITE,
 
                           STATE_WAIT_TARGET_WRITE,
 
                           STATE_WAIT_COMPLETE);
 
                           STATE_WAIT_COMPLETE);
Line 483... Line 474... 
      masterAddr_o <= (others => '0');
 
      masterAddr_o <= (others => '0');
 
      masterData_o <= (others => '0');
 
      masterData_o <= (others => '0');
 
 
 
 
 
      readContent_o <= '0';
 
      readContent_o <= '0';
 
      readFrame_o <= '0';
 
      readFrame_o <= '0';
 
      readFrameRestart_o <= '0';
 
 
 
    elsif (clk'event and clk = '1') then
 
    elsif (clk'event and clk = '1') then
 
      readContent_o <= '0';
 
      readContent_o <= '0';
 
      readFrame_o <= '0';
 
      readFrame_o <= '0';
 
      readFrameRestart_o <= '0';
 
 
 
 
 
 
 
      -- REMARK: Add support for aborted frames...
 
 
 
      case masterState is
 
      case masterState is
 
 
 
 
 
        when STATE_IDLE =>
 
        when STATE_IDLE =>
 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- Wait for a new packet or content of a new packet.
 
          -- Wait for a new packet or content of a new packet.
Line 563... Line 551... 
                masterState <= STATE_READ_PORT_LOOKUP;
 
                masterState <= STATE_READ_PORT_LOOKUP;
 
              end if;
 
              end if;
 
            else
 
            else
 
              -- Unsupported tt-value, discard the frame.
 
              -- Unsupported tt-value, discard the frame.
 
              readFrame_o <= '1';
 
              readFrame_o <= '1';
 
              masterState <= STATE_IDLE;
 
              masterState <= STATE_ERROR;
 
            end if;
 
            end if;
 
          else
 
          else
 
            -- End of frame.
 
            -- End of frame.
 
            -- The frame is too short to contain a valid frame. Discard it.
 
            -- The frame is too short to contain a valid frame. Discard it.
 
            readFrame_o <= '1';
 
            readFrame_o <= '1';
 
            masterState <= STATE_IDLE;
 
            masterState <= STATE_ERROR;
 
          end if;
 
          end if;
 
 
 
 
 
 
 
        when STATE_ERROR =>
 
 
 
          ---------------------------------------------------------------------
 
 
 
          -- Wait one tick for the packet buffer to update its outputs. Then
 
 
 
          -- start waiting for a new packet.
 
 
 
          ---------------------------------------------------------------------
 
 
 
 
 
 
 
          masterState <= STATE_IDLE;
 
 
 
 
 
        when STATE_READ_PORT_LOOKUP =>
 
        when STATE_READ_PORT_LOOKUP =>
 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
          -- Wait for the address lookup to be complete.
 
          -- Wait for the address lookup to be complete.
 
          ---------------------------------------------------------------------
 
          ---------------------------------------------------------------------
 
 
 
 
Line 992... Line 988... 
 
 
 
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- Route table access signals.
 
  -- Route table access signals.
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
 
 
 
 
  signal address0 : std_logic_vector(7 downto 0);
 
 
 
  signal address1 : std_logic_vector(7 downto 0);
 
 
 
  signal address2 : std_logic_vector(7 downto 0);
 
 
 
  signal address3 : std_logic_vector(7 downto 0);
 
 
 
 
 
 
 
  signal lookupEnable : std_logic;
 
  signal lookupEnable : std_logic;
 
  signal lookupAddress : std_logic_vector(10 downto 0);
 
  signal lookupAddress : std_logic_vector(10 downto 0);
 
  signal lookupData : std_logic_vector(7 downto 0);
 
  signal lookupData : std_logic_vector(7 downto 0);
 
  signal lookupAck : std_logic;
 
  signal lookupAck : std_logic;
 
 
 
 
Line 1815... Line 1806... 
  LookupProcess: process(clk, areset_n)
 
  LookupProcess: process(clk, areset_n)
 
  begin
 
  begin
 
    if (areset_n = '0') then
 
    if (areset_n = '0') then
 
      lookupAck <= '0';
 
      lookupAck <= '0';
 
    elsif (clk'event and clk = '1') then
 
    elsif (clk'event and clk = '1') then
 
      if ((lookupStb_i = '1') and (lookupAck = '0')) then
 
      if (lookupAck = '0') then
 
 
 
        if (lookupStb_i = '1') then
 
        lookupAck <= '1';
 
        lookupAck <= '1';
 
 
 
        end if;
 
      else
 
      else
 
        lookupAck <= '0';
 
        lookupAck <= '0';
 
      end if;
 
      end if;
 
    end if;
 
    end if;
 
  end process;
 
  end process;
Line 2338... Line 2331... 
  end process;
 
  end process;
 
 
 
 
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- Interconnection.
 
  -- Interconnection.
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  stb_o <= stb_i(selectedMaster);
 
  stb_o <= stb_i(selectedMaster) and activeCycle;
 
  addr_o <= addr_i(selectedMaster);
 
  addr_o <= addr_i(selectedMaster);
 
 
 
 
 
  Interconnect: for i in 0 to WIDTH-1 generate
 
  Interconnect: for i in 0 to WIDTH-1 generate
 
    dataM_o(i) <= dataS_i;
 
    dataM_o(i) <= dataS_i;
 
    ack_o(i) <= ack_i when (selectedMaster = i) else '0';
 
    ack_o(i) <= ack_i when (selectedMaster = i) else '0';
Line 2391... Line 2384... 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- 
-- 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
architecture SwitchPortInterconnectImpl of SwitchPortInterconnect is
 
architecture SwitchPortInterconnectImpl of SwitchPortInterconnect is
 
  --component ChipscopeIcon1 is
 
 
 
  --  port (
 
 
 
  --    CONTROL0 : inout STD_LOGIC_VECTOR ( 35 downto 0 )
 
 
 
  --    );
 
 
 
  --end component;
 
 
 
  --component ChipscopeIlaWb is
 
 
 
  --  port (
 
 
 
  --    CLK : in STD_LOGIC := 'X';
 
 
 
  --    TRIG0 : in STD_LOGIC_VECTOR ( 46 downto 0);
 
 
 
  --    CONTROL : inout STD_LOGIC_VECTOR ( 35 downto 0 ) 
 
 
  --    );
 
 
 
  --end component;
 
 
 
  --signal control : std_logic_vector(35 downto 0);
 
 
 
  --signal trig : std_logic_vector(46 downto 0);
 
 
 
 
 
 
 
  signal activeCycle : std_logic;
 
  signal activeCycle : std_logic;
 
  signal selectedMaster : natural range 0 to WIDTH-1;
 
  signal selectedMaster : natural range 0 to WIDTH-1;
 
  signal selectedSlave : natural range 0 to WIDTH-1;
 
  signal selectedSlave : natural range 0 to WIDTH-1;
 
 
 
 
 
begin
 
begin
Line 2417... Line 2395... 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- Arbitration process.
 
  -- Arbitration process.
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
 
 
 
 
  RoundRobinArbiter: process(areset_n, clk)
 
  RoundRobinArbiter: process(areset_n, clk)
 
    variable index : natural range 0 to WIDTH-1;
 
    variable index : natural range 0 to WIDTH-1 := 0;
 
  begin
 
  begin
 
    if (areset_n = '0') then
 
    if (areset_n = '0') then
 
      activeCycle <= '0';
 
      activeCycle <= '0';
 
      selectedMaster <= 0;
 
      selectedMaster <= 0;
 
    elsif (clk'event and clk = '1') then
 
    elsif (clk'event and clk = '1') then
Line 2481... Line 2459... 
 
 
 
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- Interconnection matrix.
 
  -- Interconnection matrix.
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  Interconnect: for i in 0 to WIDTH-1 generate
 
  Interconnect: for i in 0 to WIDTH-1 generate
 
    slaveCyc_o(i) <= masterCyc_i(selectedMaster) when (selectedSlave = i) else '0';
 
    slaveCyc_o(i) <= masterCyc_i(selectedMaster) when ((activeCycle = '1') and (selectedSlave = i)) else '0';
 
    slaveStb_o(i) <= masterStb_i(selectedMaster) when (selectedSlave = i) else '0';
 
    slaveStb_o(i) <= masterStb_i(selectedMaster) when ((activeCycle = '1') and (selectedSlave = i)) else '0';
 
    slaveWe_o(i) <= masterWe_i(selectedMaster);
 
    slaveWe_o(i) <= masterWe_i(selectedMaster);
 
    slaveAddr_o(i) <= masterAddr_i(selectedMaster);
 
    slaveAddr_o(i) <= masterAddr_i(selectedMaster);
 
    slaveData_o(i) <= masterData_i(selectedMaster);
 
    slaveData_o(i) <= masterData_i(selectedMaster);
 
    masterData_o(i) <= slaveData_i(selectedSlave);
 
    masterData_o(i) <= slaveData_i(selectedSlave);
 
    masterAck_o(i) <= slaveAck_i(selectedSlave) when (selectedMaster = i) else '0';
 
    masterAck_o(i) <= slaveAck_i(selectedSlave) when (selectedMaster = i) else '0';
 
  end generate;
 
  end generate;
 
 
 
 
 
  -----------------------------------------------------------------------------
 
 
 
  -- Chipscope debugging probe.
 
 
 
  -----------------------------------------------------------------------------
 
 
 
  --trig <= masterCyc_i(selectedMaster) & masterStb_i(selectedMaster) &
 
 
 
  --        masterWe_i(selectedMaster) &  masterAddr_i(selectedMaster) &
 
 
 
  --        masterData_i(selectedMaster) & slaveData_i(selectedSlave) &
 
 
 
  --        slaveAck_i(selectedSlave);
 
 
 
  --ChipscopeIconInst: ChipscopeIcon1
 
 
 
  --  port map(CONTROL0=>control);
 
 
 
  --ChipscopeIlaInst: ChipscopeIlaWb
 
 
 
  --  port map(CLK=>clk, TRIG0=>trig, CONTROL=>control);
 
 
 
 
 
 
 
end architecture;
 
end architecture;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 No newline at end of file
 
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.