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--
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-- Risc5x
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-- www.OpenCores.Org - November 2001
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--
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--
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-- This library is free software; you can distribute it and/or modify it
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-- under the terms of the GNU Lesser General Public License as published
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-- by the Free Software Foundation; either version 2.1 of the License, or
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-- (at your option) any later version.
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--
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-- This library is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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-- See the GNU Lesser General Public License for more details.
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--
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-- A RISC CPU core.
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--
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-- (c) Mike Johnson 2001. All Rights Reserved.
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-- mikej@opencores.org for support or any other issues.
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--
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-- Revision list
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--
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-- version 1.1 bug fix: Used wrong bank select bits in direct addressing mode
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-- INDF register returns 0 when indirectly read
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-- FSR bit 8 always set
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-- version 1.0 initial opencores release
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--
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use work.pkg_risc5x.all;
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use work.pkg_prims.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity CPU is
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port (
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PADDR : out std_logic_vector(10 downto 0);
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PDATA : in std_logic_vector(11 downto 0);
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PORTA_IN : in std_logic_vector(7 downto 0);
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PORTA_OUT : out std_logic_vector(7 downto 0);
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PORTA_OE_L : out std_logic_vector(7 downto 0);
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PORTB_IN : in std_logic_vector(7 downto 0);
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PORTB_OUT : out std_logic_vector(7 downto 0);
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PORTB_OE_L : out std_logic_vector(7 downto 0);
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PORTC_IN : in std_logic_vector(7 downto 0);
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PORTC_OUT : out std_logic_vector(7 downto 0);
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PORTC_OE_L : out std_logic_vector(7 downto 0);
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DEBUG_W : out std_logic_vector(7 downto 0);
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DEBUG_PC : out std_logic_vector(10 downto 0);
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DEBUG_INST : out std_logic_vector(11 downto 0);
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DEBUG_STATUS : out std_logic_vector(7 downto 0);
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RESET : in std_logic;
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CLK : in std_logic
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);
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end;
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architecture RTL of CPU is
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-- component definitions
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component IDEC is
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port (
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INST : in std_logic_vector(11 downto 0);
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ALU_ASEL : out std_logic_vector(1 downto 0);
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ALU_BSEL : out std_logic_vector(1 downto 0);
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ALU_ADDSUB : out std_logic_vector(1 downto 0);
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ALU_BIT : out std_logic_vector(1 downto 0);
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ALU_SEL : out std_logic_vector(1 downto 0);
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WWE_OP : out std_logic;
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FWE_OP : out std_logic;
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ZWE : out std_logic;
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DCWE : out std_logic;
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CWE : out std_logic;
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BDPOL : out std_logic;
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OPTION : out std_logic;
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TRIS : out std_logic
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);
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end component;
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component ALU is
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port (
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ADDSUB : in std_logic_vector(1 downto 0);
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BIT : in std_logic_vector(1 downto 0);
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SEL : in std_logic_vector(1 downto 0);
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A : in std_logic_vector(7 downto 0);
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B : in std_logic_vector(7 downto 0);
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Y : out std_logic_vector(7 downto 0);
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CIN : in std_logic;
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COUT : out std_logic;
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DCOUT : out std_logic;
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ZOUT : out std_logic
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);
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end component;
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component REGS is
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port (
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WE : in std_logic;
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RE : in std_logic;
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BANK : in std_logic_vector(1 downto 0);
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LOCATION : in std_logic_vector(4 downto 0);
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DIN : in std_logic_vector(7 downto 0);
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DOUT : out std_logic_vector(7 downto 0);
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RESET : in std_logic;
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CLK : in std_logic
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);
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end component;
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-- type/constant definitions
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constant STATUS_RESET_VALUE : std_logic_vector(7 downto 0) := x"18";
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constant OPTION_RESET_VALUE : std_logic_vector(7 downto 0) := x"3F";
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constant INDF_ADDR : std_logic_vector(2 downto 0) := "000";
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constant TMR0_ADDR : std_logic_vector(2 downto 0) := "001";
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constant PCL_ADDR : std_logic_vector(2 downto 0) := "010";
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constant STATUS_ADDR : std_logic_vector(2 downto 0) := "011";
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constant FSR_ADDR : std_logic_vector(2 downto 0) := "100";
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constant PORTA_ADDR : std_logic_vector(2 downto 0) := "101";
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constant PORTB_ADDR : std_logic_vector(2 downto 0) := "110";
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constant PORTC_ADDR : std_logic_vector(2 downto 0) := "111";
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-- signal definitions
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signal inst : std_logic_vector(11 downto 0);
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signal inst_k : std_logic_vector(7 downto 0);
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signal inst_fsel : std_logic_vector(4 downto 0);
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signal inst_d : std_logic;
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signal inst_b : std_logic_vector(2 downto 0);
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signal pc,next_pc : std_logic_vector(10 downto 0);
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signal pc_load_stack : std_logic_vector(10 downto 0);
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signal pc_write : std_logic_vector(10 downto 0);
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signal pc_call : std_logic_vector(10 downto 0);
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signal pc_goto : std_logic_vector(10 downto 0);
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signal pc_load : std_logic_vector(10 downto 0);
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signal pc_load_sel : std_logic_vector(1 downto 0);
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signal pc_inc : std_logic;
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signal stacklevel : std_logic_vector(1 downto 0);
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signal stack1,stack2 : std_logic_vector(10 downto 0);
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signal w_reg,status,fsr,tmr0 : std_logic_vector(7 downto 0);
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signal prescaler,option : std_logic_vector(7 downto 0);
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signal trisa,trisb,trisc : std_logic_vector(7 downto 0);
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signal porta_dout : std_logic_vector(7 downto 0);
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signal portb_dout : std_logic_vector(7 downto 0);
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signal portc_dout : std_logic_vector(7 downto 0);
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signal porta_din : std_logic_vector(7 downto 0);
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signal portb_din : std_logic_vector(7 downto 0);
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signal portc_din : std_logic_vector(7 downto 0);
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signal dbus,sbus : std_logic_vector(7 downto 0);
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signal sbus_swap : std_logic_vector(7 downto 0);
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signal sbus_mux_out : std_logic_vector(7 downto 0);
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-- inst decode
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signal regfile_sel,special_sel : std_logic;
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signal fileaddr_indirect : std_logic;
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signal fileaddr_mux1 : std_logic_vector(6 downto 0);
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signal fileaddr_mux0 : std_logic_vector(6 downto 0);
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signal istris,isoption : std_logic;
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signal fwe,wwe,zwe,dcwe,cwe : std_logic;
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signal bdpol : std_logic;
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signal bd : std_logic_vector(7 downto 0);
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signal skip : std_logic;
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-- alu
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signal alu_asel,alu_bsel : std_logic_vector(1 downto 0) := (others => '0');
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signal alu_addsub : std_logic_vector(1 downto 0) := (others => '0');
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signal alu_bit : std_logic_vector(1 downto 0) := (others => '0');
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signal alu_sel : std_logic_vector(1 downto 0) := (others => '0');
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signal alu_z,alu_dcout,alu_cout : std_logic := '0';
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signal alu_a,alu_b : std_logic_vector(7 downto 0) := (others => '0');
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signal alu_out : std_logic_vector(7 downto 0);
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signal regfile_we,regfile_re : std_logic;
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signal regfile_in,regfile_out : std_logic_vector(7 downto 0);
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signal fileaddr : std_logic_vector(6 downto 0);
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begin -- architecture
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u_idec : IDEC
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port map (
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INST => inst,
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ALU_ASEL => alu_asel,
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ALU_BSEL => alu_bsel,
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ALU_ADDSUB => alu_addsub,
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ALU_BIT => alu_bit,
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ALU_SEL => alu_sel,
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WWE_OP => wwe,
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FWE_OP => fwe,
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ZWE => zwe,
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DCWE => dcwe,
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CWE => cwe,
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BDPOL => bdpol,
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OPTION => isoption,
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TRIS => istris
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);
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u_alu : ALU
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port map (
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ADDSUB => alu_addsub,
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BIT => alu_bit,
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SEL => alu_sel,
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A => alu_a,
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B => alu_b,
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Y => alu_out,
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CIN => status(0),
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COUT => alu_cout,
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DCOUT => alu_dcout,
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ZOUT => alu_z
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);
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u_regs : REGS
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port map (
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WE => regfile_we,
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RE => regfile_re,
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BANK => fileaddr(6 downto 5),
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LOCATION => fileaddr(4 downto 0),
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DIN => regfile_in,
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DOUT => regfile_out,
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RESET => RESET,
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CLK => CLK
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);
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DEBUG_W <= w_reg;
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DEBUG_PC <= pc(10 downto 0);
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DEBUG_INST <= inst;
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DEBUG_STATUS <= status;
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-- *********** REGISTER FILE Addressing ****************
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p_addr_dec_comb : process(inst_fsel,fsr)
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begin
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if (inst_fsel = ("00" & INDF_ADDR)) then
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fileaddr_indirect <= '1';
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else
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fileaddr_indirect <= '0';
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end if;
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fileaddr_mux1 <= fsr(6 downto 0);
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fileaddr_mux0 <= (fsr(6 downto 5) & inst_fsel);
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end process;
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fileaddr_mux : MUX2
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generic map (
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WIDTH => 7,
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SLICE => 1,
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OP_REG => FALSE
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)
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port map (
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DIN1 => fileaddr_mux1,
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DIN0 => fileaddr_mux0,
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SEL => fileaddr_indirect,
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ENA => '0', -- not used
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CLK => '0', -- not used
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DOUT => fileaddr
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);
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p_regfile_we_comb : process(regfile_sel,fwe,alu_asel,alu_bsel)
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begin
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regfile_we <= regfile_sel and fwe;
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regfile_re <= '1'; -- not used
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end process;
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p_fileaddr_dec_comb : process(fileaddr,isoption,istris)
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begin
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regfile_sel <= '1'; -- everything else;
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special_sel <= '0';
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if (fileaddr(4 downto 3) = "00") and (isoption = '0') and (istris = '0') then
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special_sel <= '1'; -- lower 8 addresses in ALL BANKS 1 lut
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end if;
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end process;
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sbus_muxa : MUX8
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generic map (
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WIDTH => 8,
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OP_REG => FALSE
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)
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port map (
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DIN7 => portc_din,
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DIN6 => portb_din,
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DIN5 => porta_din,
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DIN4 => fsr,
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DIN3 => status,
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DIN2 => pc(7 downto 0),
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DIN1 => tmr0,
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DIN0 => x"00", -- INDF returns 0
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SEL => inst_fsel(2 downto 0),
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ENA => '0',
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CLK => '0',
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DOUT => sbus_mux_out
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);
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sbus_muxb : MUX2
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generic map (
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WIDTH => 8,
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SLICE => 1,
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OP_REG => FALSE
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)
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port map (
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DIN1 => sbus_mux_out,
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DIN0 => regfile_out,
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SEL => special_sel,
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ENA => '0',
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CLK => '0',
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DOUT => sbus
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);
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p_dbus_comb : process(alu_out)
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begin
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dbus <= alu_out;
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regfile_in <= alu_out;
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end process;
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p_paddr_comb : process(next_pc)
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begin
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PADDR <= next_pc(10 downto 0);
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end process;
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p_inst_assign_comb : process(inst)
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begin
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inst_k <= inst(7 downto 0);
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inst_fsel <= inst(4 downto 0);
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inst_d <= inst(5);
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inst_b <= inst(7 downto 5);
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end process;
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p_bdec_assign_comb : process(inst_b,bdpol)
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variable bdec : std_logic_vector(7 downto 0);
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begin
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-- 1 lut
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bdec := "00000001";
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case inst_b is
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when "000" => bdec := "00000001";
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when "001" => bdec := "00000010";
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when "010" => bdec := "00000100";
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when "011" => bdec := "00001000";
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when "100" => bdec := "00010000";
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when "101" => bdec := "00100000";
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when "110" => bdec := "01000000";
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when "111" => bdec := "10000000";
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when others => null;
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end case;
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if (bdpol = '1') then
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bd <= not bdec;
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else
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bd <= bdec;
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end if;
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end process;
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p_inst : process(CLK,RESET)
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begin
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if (RESET = '1') then
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inst <= x"000";
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elsif CLK'event and (CLK = '1') then
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if (skip = '1') then
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inst <= x"000"; -- force NOP
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else
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inst <= PDATA;
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end if;
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end if;
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end process;
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p_skip_comb : process(inst,alu_z,fwe,special_sel,fileaddr)
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begin
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-- SKIP signal.
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-- We want to insert the NOP instruction for the following conditions:
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-- we have modified PCL
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-- GOTO,CALL and RETLW instructions
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-- BTFSS instruction when aluz is HI
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-- BTFSC instruction when aluz is LO
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skip <= '0';
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if (fwe = '1') and (special_sel = '1') and (fileaddr(2 downto 0) = PCL_ADDR) then skip <= '1'; end if;
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if (inst(11 downto 10) = "10") then skip <= '1'; end if;
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if (inst(11 downto 8) = "0110") and (alu_z = '1') then skip <= '1'; end if; -- BTFSC
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if (inst(11 downto 8) = "0111") and (alu_z = '0') then skip <= '1'; end if; -- BTFSS
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if (inst(11 downto 6) = "001011") and (alu_z = '1') then skip <= '1'; end if; -- DECFSZ
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if (inst(11 downto 6) = "001111") and (alu_z = '1') then skip <= '1'; end if; -- INCFSZ
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end process;
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sbus_swap <= sbus(3 downto 0) & sbus(7 downto 4);
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alua_mux : MUX4
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generic map (
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WIDTH => 8,
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SLICE => 1,
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OP_REG => FALSE
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)
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port map (
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DIN3 => sbus_swap,
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DIN2 => inst_k,
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DIN1 => sbus,
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DIN0 => w_reg,
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SEL => alu_asel,
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ENA => '0',
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CLK => '0',
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DOUT => alu_a
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);
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alub_mux : MUX4
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generic map (
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WIDTH => 8,
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SLICE => 0,
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OP_REG => FALSE
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)
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port map (
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DIN3 => x"01",
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DIN2 => bd,
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DIN1 => sbus,
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DIN0 => w_reg,
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SEL => alu_bsel,
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ENA => '0',
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CLK => '0',
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DOUT => alu_b
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);
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p_w_reg : process(CLK,RESET)
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begin
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if (RESET = '1') then
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w_reg <= x"00";
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elsif CLK'event and (CLK = '1') then
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if (wwe = '1') then
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w_reg <= dbus;
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end if;
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end if;
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end process;
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p_tmr0 : process(CLK,RESET)
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variable mask : std_logic_vector(7 downto 0);
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begin
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if (RESET = '1') then
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tmr0 <= x"00";
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elsif CLK'event and (CLK = '1') then
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-- See if the timer register is actually being written to
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if (fwe = '1') and (special_sel = '1') and (fileaddr(2 downto 0) = TMR0_ADDR) then
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tmr0 <= dbus;
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else
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mask := "00000001";
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case option(2 downto 0) is
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when "000" => mask := "00000001";
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when "001" => mask := "00000011";
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when "010" => mask := "00000111";
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when "011" => mask := "00001111";
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when "100" => mask := "00011111";
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when "101" => mask := "00111111";
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when "110" => mask := "01111111";
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when "111" => mask := "11111111";
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when others => null;
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end case;
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if ((prescaler and mask) = "00000000") or (option(3) = '1') then
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tmr0 <= tmr0 + "1";
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end if;
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end if;
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end if;
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end process;
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p_prescaler : process(CLK,RESET)
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begin
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if (RESET = '1') then
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prescaler <= x"00";
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elsif CLK'event and (CLK = '1') then
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if not (option(5) = '1') then
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prescaler <= prescaler + "1";
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end if;
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end if;
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end process;
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p_status_reg : process(CLK,RESET)
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variable new_z,new_dc,new_c : std_logic;
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begin
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if (RESET = '1') then
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status <= STATUS_RESET_VALUE;
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elsif CLK'event and (CLK = '1') then
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-- See if the status register is actually being written to
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|
-- this is not accurate, bits 4 & 3 should be read only
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-- additionally, zwe,cwe and dcwe should override fwe
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if (fwe = '1') and (special_sel = '1') and (fileaddr(2 downto 0) = STATUS_ADDR) then
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|
status <= dbus;
|
|
else
|
|
-- For the carry and zero flags, each instruction has its own rule as
|
|
-- to whether to update this flag or not. The instruction decoder is
|
|
-- providing us with an enable for C and Z. Use this to decide whether
|
|
-- to retain the existing value, or update with the new alu status output.
|
|
if (zwe = '1') then new_z := alu_z; else new_z := status(2); end if;
|
|
if (dcwe = '1') then new_dc := alu_dcout; else new_dc := status(1); end if;
|
|
if (cwe = '1') then new_c := alu_cout; else new_c := status(0); end if;
|
|
status <= (
|
|
status(7) & -- BIT 7: Undefined.. (maybe use for debugging)
|
|
status(6) & -- BIT 6: Program Page, HI bit
|
|
status(5) & -- BIT 5: Program Page, LO bit
|
|
status(4) & -- BIT 4: Time Out bit (not implemented at this time)
|
|
status(3) & -- BIT 3: Power Down bit (not implemented at this time)
|
|
new_z & -- BIT 2: Z
|
|
new_dc & -- BIT 1: DC
|
|
new_c); -- BIT 0: C
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
p_fsr_reg : process(CLK,RESET)
|
|
begin
|
|
if (RESET = '1') then
|
|
fsr <= x"80";
|
|
elsif CLK'event and (CLK = '1') then
|
|
if (fwe = '1') and (special_sel = '1') and (fileaddr(2 downto 0) = FSR_ADDR) then
|
|
fsr <= dbus;
|
|
end if;
|
|
fsr(7) <= '1'; --always set in real chip
|
|
end if;
|
|
end process;
|
|
|
|
p_option_reg : process(CLK,RESET)
|
|
begin
|
|
if (RESET = '1') then
|
|
option <= OPTION_RESET_VALUE;
|
|
elsif CLK'event and (CLK = '1') then
|
|
if (isoption = '1') then
|
|
option <= dbus;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
p_drive_ports_comb : process(porta_dout,trisa,portb_dout,trisb,portc_dout,trisc)
|
|
begin
|
|
PORTA_OE_L <= trisa;
|
|
PORTB_OE_L <= trisb;
|
|
PORTC_OE_L <= trisc;
|
|
|
|
PORTA_OUT <= porta_dout;
|
|
PORTB_OUT <= portb_dout;
|
|
PORTC_OUT <= portc_dout;
|
|
|
|
end process;
|
|
|
|
port_in : process(CLK,RESET,PORTA_IN,PORTB_IN,PORTC_IN)
|
|
begin
|
|
-- the input registers don't exist in the real device,
|
|
-- so if you read an output we have introduced a clock delay.
|
|
if (RESET = '1') then
|
|
porta_din <= (others => '0');
|
|
portb_din <= (others => '0');
|
|
portc_din <= (others => '0');
|
|
elsif CLK'event and (CLK = '1') then -- comment this out for combinatorial ip
|
|
--else -- or comment this for registered ip
|
|
porta_din <= PORTA_IN;
|
|
portb_din <= PORTB_IN;
|
|
portc_din <= PORTC_IN;
|
|
end if;
|
|
end process;
|
|
|
|
p_port_reg : process(CLK,RESET)
|
|
begin
|
|
if (RESET = '1') then
|
|
trisa <= x"FF"; -- default tristate
|
|
trisb <= x"FF"; -- default tristate
|
|
trisc <= x"FF"; -- default tristate
|
|
porta_dout <= x"00";
|
|
portb_dout <= x"00";
|
|
portc_dout <= x"00";
|
|
elsif CLK'event and (CLK = '1') then
|
|
|
|
if (fwe = '1') and (fileaddr(2 downto 0) = PORTA_ADDR) then
|
|
if (istris = '0') and (special_sel = '1') then
|
|
porta_dout <= dbus;
|
|
elsif (istris = '1') then
|
|
trisa <= dbus;
|
|
end if;
|
|
end if;
|
|
|
|
if (fwe = '1') and (fileaddr(2 downto 0) = PORTB_ADDR) then
|
|
if (istris = '0') and (special_sel = '1') then
|
|
portb_dout <= dbus;
|
|
elsif (istris = '1') then
|
|
trisb <= dbus;
|
|
end if;
|
|
end if;
|
|
|
|
if (fwe = '1') and (fileaddr(2 downto 0) = PORTC_ADDR) then
|
|
if (istris = '0') and (special_sel = '1') then
|
|
portc_dout <= dbus;
|
|
elsif (istris = '1') then
|
|
trisc <= dbus;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
-- ********** PC AND STACK *************************
|
|
|
|
p_next_pc_comb : process(pc,inst,status,stacklevel,stack1,stack2,dbus,fileaddr,special_sel,fwe)
|
|
begin
|
|
|
|
pc_goto <= ( status(6 downto 5) & inst(8 downto 0));
|
|
pc_call <= ( status(6 downto 5) & '0' & inst(7 downto 0));
|
|
pc_write <= (pc(10) & '0' & pc(8) & dbus); -- set bit 9 to zero
|
|
|
|
pc_inc <= '1'; -- default
|
|
|
|
pc_load_sel <= "00"; -- pc write
|
|
if (fwe = '1') and (special_sel = '1') and (fileaddr(2 downto 0) = PCL_ADDR) then
|
|
--pc_load_sel <= "00"; default
|
|
pc_inc <= '0'; -- as we have modified next_pc, must skip next instruction
|
|
end if;
|
|
|
|
if (inst(11 downto 9) = "101") then pc_load_sel <= "01"; pc_inc <= '0'; end if; -- goto
|
|
if (inst(11 downto 8) = "1001") then pc_load_sel <= "10"; pc_inc <= '0'; end if; -- call
|
|
if (inst(11 downto 8) = "1000") then pc_load_sel <= "11"; pc_inc <= '0'; end if; -- ret
|
|
|
|
end process;
|
|
|
|
pc_load_mux : MUX4
|
|
generic map (
|
|
WIDTH => 11,
|
|
SLICE => 0,
|
|
OP_REG => FALSE
|
|
)
|
|
port map (
|
|
DIN3 => pc_load_stack,
|
|
DIN2 => pc_call,
|
|
DIN1 => pc_goto,
|
|
DIN0 => pc_write,
|
|
|
|
SEL => pc_load_sel,
|
|
ENA => '0',
|
|
CLK => '0',
|
|
|
|
DOUT => pc_load
|
|
);
|
|
|
|
pc_mux2_add_reg : MUX2_ADD_REG
|
|
generic map (
|
|
WIDTH => 11
|
|
)
|
|
port map (
|
|
ADD_VAL => "00000000001", -- pc = pc + 1
|
|
LOAD_VAL => pc_load, -- branch
|
|
|
|
ADD => pc_inc,
|
|
|
|
PRESET => RESET,
|
|
ENA => '1',
|
|
CLK => CLK,
|
|
|
|
DOUT => next_pc,
|
|
REG_DOUT => pc
|
|
);
|
|
|
|
p_stack_comb : process(stacklevel,stack1,stack2)
|
|
begin
|
|
pc_load_stack <= stack1; -- default
|
|
case stacklevel is
|
|
when "00" => pc_load_stack <= stack1;
|
|
when "01" => pc_load_stack <= stack1;
|
|
when "10" => pc_load_stack <= stack2;
|
|
when "11" => pc_load_stack <= stack2;
|
|
when others => null;
|
|
end case;
|
|
end process;
|
|
|
|
p_stack_reg : process(CLK,RESET)
|
|
begin
|
|
if (RESET = '1') then
|
|
stack1 <= (others => '0');
|
|
stack2 <= (others => '0');
|
|
elsif CLK'event and (CLK = '1') then
|
|
if (inst(11 downto 8) = "1001") then
|
|
case stacklevel is
|
|
when "00" => stack1 <= pc(10 downto 0);
|
|
when "01" => stack2 <= pc(10 downto 0);
|
|
when "10" => assert false report "Too many CALLs !" severity failure;
|
|
when "11" => assert false report "Too many CALLs !" severity failure;
|
|
when others => null;
|
|
end case;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
p_stack_level : process(CLK,RESET)
|
|
begin
|
|
if (RESET = '1') then
|
|
stacklevel <= "00";
|
|
elsif CLK'event and (CLK = '1') then
|
|
stacklevel <= stacklevel;
|
|
if (inst(11 downto 8) = "1001") then
|
|
case stacklevel is
|
|
when "00" => stacklevel <="01"; -- 1st call
|
|
when "01" => stacklevel <="10"; -- 2nd call
|
|
when "10" => stacklevel <="10"; -- already 2, ignore
|
|
when "11" => stacklevel <="00"; -- broke
|
|
when others => null;
|
|
end case;
|
|
elsif (inst(11 downto 8) = "1000") then
|
|
case stacklevel is
|
|
when "00" => stacklevel <="00"; -- broke
|
|
when "01" => stacklevel <="00"; -- go back to no call
|
|
when "10" => stacklevel <="01"; -- go back to 1 call
|
|
when "11" => stacklevel <="10"; -- broke
|
|
when others => null;
|
|
end case;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
end rtl;
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
