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--
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-- Risc5x
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-- www.OpenCores.Org - November 2001
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--
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--
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-- This library is free software; you can distribute it and/or modify it
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-- under the terms of the GNU Lesser General Public License as published
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-- by the Free Software Foundation; either version 2.1 of the License, or
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-- (at your option) any later version.
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--
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-- This library is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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-- See the GNU Lesser General Public License for more details.
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--
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-- A RISC CPU core.
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--
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-- (c) Mike Johnson 2001. All Rights Reserved.
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-- mikej@opencores.org for support or any other issues.
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--
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-- Revision list
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--
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-- version 1.0 initial opencores release
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--
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use work.pkg_risc5x.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity IDEC is
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port (
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INST : in std_logic_vector(11 downto 0);
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ALU_ASEL : out std_logic_vector(1 downto 0);
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ALU_BSEL : out std_logic_vector(1 downto 0);
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ALU_ADDSUB : out std_logic_vector(1 downto 0);
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ALU_BIT : out std_logic_vector(1 downto 0);
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ALU_SEL : out std_logic_vector(1 downto 0);
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WWE_OP : out std_logic;
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FWE_OP : out std_logic;
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ZWE : out std_logic;
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DCWE : out std_logic;
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CWE : out std_logic;
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BDPOL : out std_logic;
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OPTION : out std_logic;
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TRIS : out std_logic
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);
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end;
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architecture RTL of IDEC is
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-- signal definitions
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signal alu : std_logic_vector(9 downto 0) := (others => '0');
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signal flags : std_logic_vector(2 downto 0) := (others => '0');
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signal fwe : std_logic;
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signal wwe : std_logic;
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signal we : std_logic;
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begin -- architecture
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-- aluasel, Select source for ALU A input. 00=W, 01=SBUS, 10=K , 11= SBUS_SWAP
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-- alubsel, Select source for ALU B input. 00=W, 01=SBUS, 10=BD, 11= "1"
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-- bit 0 : A and B, 1 : A or B, 2 : A xor B, 3 : not A
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-- wwe, W register Write Enable
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-- fwe, File Register Write Enable
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-- zwe, Status register Z bit update
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-- dcwe Status register DC bit update
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-- cwe, Status register C bit update
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-- bdpol, Polarity on bit decode vector (0=no inversion, 1=invert)
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-- tris, Instruction is an TRIS instruction
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-- option Instruction is an OPTION instruction
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p_inst_decode_comb : process(INST)
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begin
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BDPOL <= '0';
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OPTION <= '0';
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TRIS <= '0';
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alu <= (others => '0');
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flags <= (others => '0');
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fwe <= '0';
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wwe <= '0';
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we <= '0';
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case INST(11 downto 8) is
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when "0000" => --asel bsel +- bit sel
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if (INST(7 downto 0) = "00000000") then alu <= "00" & "00" & "00" & "00" & "00"; end if; -- NOP
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if (INST(7 downto 0) = "00000010") then alu <= "00" & "00" & "00" & "00" & "00"; fwe <= '1'; OPTION <= '1'; end if; -- OPTION
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if (INST(7 downto 0) = "00000011") then alu <= "00" & "00" & "00" & "00" & "00"; end if; -- SLEEP
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if (INST(7 downto 0) = "00000100") then alu <= "00" & "00" & "00" & "00" & "00"; end if; -- CLRWDT
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if (INST(7 downto 0) = "00000101") then alu <= "00" & "00" & "00" & "00" & "00"; fwe <= '1'; TRIS <= '1'; end if; -- TRIS 5
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if (INST(7 downto 0) = "00000110") then alu <= "00" & "00" & "00" & "00" & "00"; fwe <= '1'; TRIS <= '1'; end if; -- TRIS 6
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if (INST(7 downto 0) = "00000111") then alu <= "00" & "00" & "00" & "00" & "00"; fwe <= '1'; TRIS <= '1'; end if; -- TRIS 7
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if (INST(7 downto 5) = "001" ) then alu <= "00" & "00" & "00" & "00" & "00"; fwe <= '1'; end if; -- MOVWF
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if (INST(7 downto 0) = "01000000") then alu <= "00" & "00" & "00" & "10" & "01"; wwe <= '1'; flags <= "100"; end if; -- CLRW
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if (INST(7 downto 5) = "011" ) then alu <= "00" & "00" & "00" & "10" & "01"; fwe <= '1'; flags <= "100"; end if; -- CLRF
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if (INST(7 downto 6) = "10" ) then alu <= "01" & "00" & "11" & "00" & "00"; we <= '1'; flags <= "111"; end if; -- SUBWF
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if (INST(7 downto 6) = "11" ) then alu <= "01" & "11" & "11" & "00" & "00"; we <= '1'; flags <= "100"; end if; -- DECF
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when "0001" =>
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case INST(7 downto 6) is
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when "00" => alu <= "00" & "01" & "00" & "01" & "01"; we <= '1'; flags <= "100"; -- IORWF
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when "01" => alu <= "00" & "01" & "00" & "00" & "01"; we <= '1'; flags <= "100"; -- ANDWF
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when "10" => alu <= "00" & "01" & "00" & "10" & "01"; we <= '1'; flags <= "100"; -- XORWF
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when "11" => alu <= "00" & "01" & "10" & "00" & "00"; we <= '1'; flags <= "111"; -- ADDWF
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when others => null;
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end case;
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when "0010" =>
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case INST(7 downto 6) is
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when "00" => alu <= "01" & "00" & "00" & "00" & "00"; we <= '1'; flags <= "100"; -- MOVF
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when "01" => alu <= "01" & "00" & "00" & "11" & "01"; we <= '1'; flags <= "100"; -- COMF
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when "10" => alu <= "01" & "11" & "10" & "00" & "00"; we <= '1'; flags <= "100"; -- INCF
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when "11" => alu <= "01" & "11" & "11" & "00" & "00"; we <= '1'; flags <= "000"; -- DECFSZ
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when others => null;
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end case;
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when "0011" =>
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case INST(7 downto 6) is
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when "00" => alu <= "01" & "00" & "00" & "00" & "10"; we <= '1'; flags <= "001"; -- RRF
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when "01" => alu <= "01" & "00" & "00" & "00" & "11"; we <= '1'; flags <= "001"; -- RLF
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when "10" => alu <= "11" & "00" & "00" & "00" & "00"; we <= '1'; flags <= "000"; -- SWAPF
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when "11" => alu <= "01" & "11" & "10" & "00" & "00"; we <= '1'; flags <= "000"; -- INCFSZ
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when others => null;
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end case;
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when "0100" => alu <= "01" & "10" & "00" & "00" & "01"; fwe <= '1'; flags <= "000"; BDPOL <= '1'; -- BCF
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when "0101" => alu <= "01" & "10" & "00" & "01" & "01"; fwe <= '1'; flags <= "000"; -- BSF
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when "0110" => alu <= "01" & "10" & "00" & "00" & "01"; -- BTFSC
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when "0111" => alu <= "01" & "10" & "00" & "00" & "01"; -- BTFSS
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when "1000" => alu <= "10" & "00" & "00" & "00" & "00"; wwe <= '1'; -- RETLW
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when "1001" => alu <= "10" & "00" & "00" & "00" & "00"; -- CALL
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when "1010" => alu <= "10" & "00" & "00" & "00" & "00"; -- GOTO
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when "1011" => alu <= "10" & "00" & "00" & "00" & "00"; -- GOTO
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when "1100" => alu <= "10" & "00" & "00" & "00" & "00"; wwe <= '1'; flags <= "000"; -- MOVLW
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when "1101" => alu <= "10" & "00" & "00" & "01" & "01"; wwe <= '1'; flags <= "100"; -- IORLW
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when "1110" => alu <= "10" & "00" & "00" & "00" & "01"; wwe <= '1'; flags <= "100"; -- ANDLW
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when "1111" => alu <= "10" & "00" & "00" & "10" & "01"; wwe <= '1'; flags <= "100"; -- XORLW
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when others => null;
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end case;
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end process;
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p_we_comb : process(wwe,fwe,we,INST)
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begin
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WWE_OP <= '0';
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FWE_OP <= '0';
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if (wwe = '1') or ((we = '1') and (INST(5) ='0')) then
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WWE_OP <= '1';
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end if;
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if (fwe = '1') or ((we = '1') and (INST(5) = '1')) then
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FWE_OP <= '1';
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end if;
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end process;
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ALU_ASEL <= alu(9 downto 8);
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ALU_BSEL <= alu(7 downto 6);
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ALU_ADDSUB <= alu(5 downto 4);
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ALU_BIT <= alu(3 downto 2);
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ALU_SEL <= alu(1 downto 0);
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ZWE <= flags(2);
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DCWE <= flags(1);
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CWE <= flags(0);
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end rtl;
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