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--
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-- Risc5x
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-- www.OpenCores.Org - November 2001
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--
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--
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-- This library is free software; you can distribute it and/or modify it
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-- under the terms of the GNU Lesser General Public License as published
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-- by the Free Software Foundation; either version 2.1 of the License, or
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-- (at your option) any later version.
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--
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-- This library is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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-- See the GNU Lesser General Public License for more details.
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--
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-- A RISC CPU core.
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--
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-- (c) Mike Johnson 2001. All Rights Reserved.
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-- mikej@opencores.org for support or any other issues.
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--
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-- Revision list
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--
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-- version 1.0 initial opencores release
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity MUX8 is
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generic (
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WIDTH : in natural := 8;
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OP_REG : in boolean := FALSE
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);
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port (
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DIN7 : in std_logic_vector(WIDTH-1 downto 0);
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DIN6 : in std_logic_vector(WIDTH-1 downto 0);
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DIN5 : in std_logic_vector(WIDTH-1 downto 0);
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DIN4 : in std_logic_vector(WIDTH-1 downto 0);
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DIN3 : in std_logic_vector(WIDTH-1 downto 0);
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DIN2 : in std_logic_vector(WIDTH-1 downto 0);
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DIN1 : in std_logic_vector(WIDTH-1 downto 0);
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DIN0 : in std_logic_vector(WIDTH-1 downto 0);
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SEL : in std_logic_vector(2 downto 0);
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ENA : in std_logic;
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CLK : in std_logic;
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DOUT : out std_logic_vector(WIDTH-1 downto 0)
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);
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end;
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--
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-- USE THIS ARCHITECTURE FOR XILINX
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--
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use work.pkg_xilinx_prims.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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architecture VIRTEX of MUX8 is
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signal dout_int : std_logic_vector(WIDTH-1 downto 0);
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signal mux8_01 : std_logic_vector(WIDTH-1 downto 0);
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signal mux8_23 : std_logic_vector(WIDTH-1 downto 0);
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signal mux8_45 : std_logic_vector(WIDTH-1 downto 0);
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signal mux8_67 : std_logic_vector(WIDTH-1 downto 0);
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signal mux8_03 : std_logic_vector(WIDTH-1 downto 0);
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signal mux8_47 : std_logic_vector(WIDTH-1 downto 0);
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begin -- architecture
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ram_bit : for i in 0 to WIDTH-1 generate
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attribute RLOC of mux8_lut1,mux8_lut2 : label is "R" & integer'image((WIDTH -1)-i) & "C0.S1";
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attribute RLOC of mux8_lut3,mux8_lut4 : label is "R" & integer'image((WIDTH -1)-i) & "C0.S0";
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attribute RLOC of mux8_muxf5_1 : label is "R" & integer'image((WIDTH -1)-i) & "C0.S1";
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attribute RLOC of mux8_muxf5_2 : label is "R" & integer'image((WIDTH -1)-i) & "C0.S0";
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attribute RLOC of mux8_muxf6_1 : label is "R" & integer'image((WIDTH -1)-i) & "C0.S0";
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attribute INIT of mux8_lut1 : label is "00CA";
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attribute INIT of mux8_lut2 : label is "00CA";
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attribute INIT of mux8_lut3 : label is "00CA";
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attribute INIT of mux8_lut4 : label is "00CA";
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begin
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mux8_lut1: LUT4
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--pragma translate_off
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generic map (
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INIT => str2slv(mux8_lut1'INIT)
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)
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--pragma translate_on
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port map (
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I0 => DIN0(i),
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I1 => DIN1(i),
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I2 => SEL(0),
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I3 => '0',
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O => mux8_01(i));
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mux8_lut2: LUT4
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--pragma translate_off
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generic map (
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INIT => str2slv(mux8_lut2'INIT)
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)
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--pragma translate_on
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port map (
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I0 => DIN2(i),
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I1 => DIN3(i),
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I2 => SEL(0),
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I3 => '0',
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O => mux8_23(i));
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mux8_lut3: LUT4
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--pragma translate_off
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generic map (
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INIT => str2slv(mux8_lut3'INIT)
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)
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--pragma translate_on
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port map (
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I0 => DIN4(i),
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I1 => DIN5(i),
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I2 => SEL(0),
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I3 => '0',
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O => mux8_45(i));
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mux8_lut4: LUT4
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--pragma translate_off
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generic map (
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INIT => str2slv(mux8_lut4'INIT)
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)
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--pragma translate_on
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port map (
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I0 => DIN6(i),
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I1 => DIN7(i),
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I2 => SEL(0),
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I3 => '0',
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O => mux8_67(i));
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mux8_muxf5_1 : MUXF5
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port map (
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O => mux8_03(i),
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I0 => mux8_01(i),
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I1 => mux8_23(i),
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S => SEL(1));
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mux8_muxf5_2 : MUXF5
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port map (
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O => mux8_47(i),
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I0 => mux8_45(i),
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I1 => mux8_67(i),
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S => SEL(1));
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mux8_muxf6_1 : MUXF6
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port map (
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O => dout_int(i),
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I0 => mux8_03(i),
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I1 => mux8_47(i),
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S => SEL(2));
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opreg : if OP_REG generate
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attribute RLOC of reg : label is "R" & integer'image((WIDTH -1)-i) & "C0.S1";
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begin
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reg : FDE
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port map (
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D => dout_int(i),
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C => CLK,
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CE => ENA,
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Q => DOUT(i));
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end generate;
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opwire : if not OP_REG generate
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DOUT(i) <= dout_int(i);
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end generate;
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end generate;
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end VIRTEX;
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--pragma translate_off
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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architecture RTL of MUX8 is
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signal mux : std_logic_vector(WIDTH-1 downto 0);
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begin -- architecture
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p_mux_comb : process(DIN0,DIN1,DIN2,DIN3,DIN4,DIN5,DIN6,DIN7,SEL)
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variable ram_addr : integer := 0;
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begin
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mux <= DIN0;
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case SEL is
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when "000" => mux <= DIN0;
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when "001" => mux <= DIN1;
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when "010" => mux <= DIN2;
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when "011" => mux <= DIN3;
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when "100" => mux <= DIN4;
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when "101" => mux <= DIN5;
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when "110" => mux <= DIN6;
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when "111" => mux <= DIN7;
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when others => null;
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end case;
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end process;
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opreg : if OP_REG generate
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p_opreg : process
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begin
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wait until CLK'event and (CLK = '1');
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if (ENA = '1') then
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DOUT <= mux;
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end if;
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end process;
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end generate;
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opwire : if not OP_REG generate
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DOUT <= mux;
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end generate;
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end RTL;
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--pragma translate_on
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No newline at end of file
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No newline at end of file
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