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--
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-- Risc5x
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-- www.OpenCores.Org - November 2001
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--
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--
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-- This library is free software; you can distribute it and/or modify it
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-- under the terms of the GNU Lesser General Public License as published
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-- by the Free Software Foundation; either version 2.1 of the License, or
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-- (at your option) any later version.
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--
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-- This library is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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-- See the GNU Lesser General Public License for more details.
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--
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-- A RISC CPU core.
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--
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-- (c) Mike Johnson 2001. All Rights Reserved.
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-- mikej@opencores.org for support or any other issues.
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--
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-- Revision list
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--
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-- version 1.0 initial opencores release
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--
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library ieee;
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use ieee.std_logic_1164.all;
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package pkg_risc5x is
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function slv_to_integer(x : std_logic_vector) return integer;
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function integer_to_slv(n, bits : integer) return std_logic_vector;
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end;
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package body pkg_risc5x is
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function slv_to_integer(x : std_logic_vector) return integer is
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variable n : integer := 0;
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variable failure : boolean := false;
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begin
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assert (x'high - x'low + 1) <= 31
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report "Range of sulv_to_integer argument exceeds integer range"
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severity error;
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for i in x'range loop
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n := n * 2;
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case x(i) is
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when '1' | 'H' => n := n + 1;
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when '0' | 'L' => null;
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when others =>
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-- failure := true;
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null;
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end case;
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end loop;
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assert not failure
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report "sulv_to_integer cannot convert indefinite std_logic_vector"
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severity error;
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if failure then
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return 0;
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else
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return n;
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end if;
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end slv_to_integer;
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function integer_to_slv(n, bits : integer) return std_logic_vector is
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variable x : std_logic_vector(bits-1 downto 0) := (others => '0');
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variable tempn : integer := n;
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begin
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for i in x'reverse_range loop
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if (tempn mod 2) = 1 then
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x(i) := '1';
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end if;
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tempn := tempn / 2;
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end loop;
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return x;
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end integer_to_slv;
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end;
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