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#--
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#-- Risc5x
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#-- www.OpenCores.Org - November 2001
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#--
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#--
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#-- This library is free software; you can distribute it and/or modify it
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#-- under the terms of the GNU Lesser General Public License as published
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#-- by the Free Software Foundation; either version 2.1 of the License, or
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#-- (at your option) any later version.
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#--
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#-- This library is distributed in the hope that it will be useful, but
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#-- WITHOUT ANY WARRANTY; without even the implied warranty of
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#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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#-- See the GNU Lesser General Public License for more details.
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#--
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#-- A RISC CPU core.
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#--
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#-- (c) Mike Johnson 2001. All Rights Reserved.
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#-- mikej@opencores.org for support or any other issues.
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#--
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#-- Revision list
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#--
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#-- version 1.0 initial opencores release
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#--
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CONFIG PART = XCV300E-FG456-8 ;
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NET CLK TNM_NET = clk_cpu;
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TIMESPEC TS1 =PERIOD:clk_cpu : 25 ns;
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TIMESPEC TS11=FROM:PADS:TO:FFS : 8ns;
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TIMESPEC TS12=FROM:FFS:TO:PADS : 8ns;
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AREA_GROUP RISC_GRP RANGE = CLB_R20C1:CLB_R32C10 ;
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INST U0 AREA_GROUP = RISC_GRP ;
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INST U0/PC_MUX2_ADD_REG RLOC_ORIGIN=R27C1;
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INST U0/PC_LOAD_MUX RLOC_ORIGIN=R22C1;
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INST U0/FILEADDR_MUX RLOC_ORIGIN=R26C2;
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INST U0/U_REGS RLOC_ORIGIN=R25C2;
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INST U0/SBUS_MUXA RLOC_ORIGIN=R25C6;
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INST U0/SBUS_MUXB RLOC_ORIGIN=R25C7;
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INST U0/ALUA_MUX RLOC_ORIGIN=R25C8;
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INST U0/ALUB_MUX RLOC_ORIGIN=R25C8;
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INST U0/U_ALU/U_ADD_SUB RLOC_ORIGIN=R25C9;
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INST U0/U_ALU/U_ALUBIT RLOC_ORIGIN=R29C9;
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INST U0/U_ALU/U_MUX4 RLOC_ORIGIN=R24C9;
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