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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* @brief CPU functional simulator class definition.
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* @brief CPU functional simulator class definition.
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*/
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*/
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#include "api_core.h"
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#include <api_core.h>
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#include "cpu_riscv_func.h"
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#include "cpu_riscv_func.h"
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#include "riscv-isa.h"
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#if 1
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#include "coreservices/iserial.h"
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#endif
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namespace debugger {
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namespace debugger {
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void addIsaUserRV64I(CpuContextType *data, AttributeType *out);
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CpuRiver_Functional::CpuRiver_Functional(const char *name) :
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void addIsaPrivilegedRV64I(CpuContextType *data, AttributeType *out);
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CpuGeneric(name),
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void addIsaExtensionA(CpuContextType *data, AttributeType *out);
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portRegs_(this, "regs", DSUREG(ureg.v.iregs), Reg_Total),
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void addIsaExtensionF(CpuContextType *data, AttributeType *out);
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portSavedRegs_(this, "savedregs", 0, Reg_Total), // not mapped !!!
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void addIsaExtensionM(CpuContextType *data, AttributeType *out);
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portCSR_(this, "csr", DSUREG(csr), 1<<12) {
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void generateException(uint64_t code, CpuContextType *data);
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void generateInterrupt(uint64_t code, CpuContextType *data);
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uint64_t readCSR(uint32_t idx, CpuContextType *data);
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void writeCSR(uint32_t idx, uint64_t val, CpuContextType *data);
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CpuRiscV_Functional::CpuRiscV_Functional(const char *name)
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: IService(name), IHap(HAP_ConfigDone) {
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registerInterface(static_cast<IThread *>(this));
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registerInterface(static_cast<ICpuRiscV *>(this));
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registerInterface(static_cast<ICpuRiscV *>(this));
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registerInterface(static_cast<IClock *>(this));
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registerInterface(static_cast<IHap *>(this));
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registerAttribute("Enable", &isEnable_);
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registerAttribute("Bus", &bus_);
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registerAttribute("ListExtISA", &listExtISA_);
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registerAttribute("ListExtISA", &listExtISA_);
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registerAttribute("FreqHz", &freqHz_);
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registerAttribute("VendorID", &vendorID_);
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registerAttribute("GenerateRegTraceFile", &generateRegTraceFile_);
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registerAttribute("VectorTable", &vectorTable_);
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registerAttribute("GenerateMemTraceFile", &generateMemTraceFile_);
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}
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registerAttribute("ResetVector", &resetVector_);
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CpuRiver_Functional::~CpuRiver_Functional() {
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isEnable_.make_boolean(true);
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bus_.make_string("");
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listExtISA_.make_list(0);
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freqHz_.make_uint64(1);
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generateRegTraceFile_.make_boolean(false);
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generateMemTraceFile_.make_boolean(false);
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resetVector_.make_uint64(0x1000);
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cpu_context_.step_cnt = 0;
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cpu_context_.stack_trace_cnt = 0;
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RISCV_event_create(&config_done_, "riscv_func_config_done");
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RISCV_register_hap(static_cast<IHap *>(this));
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cpu_context_.reset = true;
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dbg_state_ = STATE_Normal;
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last_hit_breakpoint_ = ~0;
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reset();
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trans_.source_idx = CFG_NASTI_MASTER_CACHED;
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cpu_context_.reg_trace_file = 0;
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cpu_context_.mem_trace_file = 0;
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dport.valid = 0;
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}
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CpuRiscV_Functional::~CpuRiscV_Functional() {
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CpuContextType *pContext = getpContext();
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if (pContext->reg_trace_file) {
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pContext->reg_trace_file->close();
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delete pContext->reg_trace_file;
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}
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if (pContext->mem_trace_file) {
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pContext->mem_trace_file->close();
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delete pContext->mem_trace_file;
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}
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RISCV_event_close(&config_done_);
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}
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void CpuRiscV_Functional::postinitService() {
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CpuContextType *pContext = getpContext();
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pContext->ibus = static_cast<IBus *>(
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RISCV_get_service_iface(bus_.to_string(), IFACE_BUS));
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if (!pContext->ibus) {
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RISCV_error("Bus interface '%s' not found",
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bus_.to_string());
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return;
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}
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}
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void CpuRiver_Functional::postinitService() {
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// Supported instruction sets:
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// Supported instruction sets:
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for (int i = 0; i < INSTR_HASH_TABLE_SIZE; i++) {
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for (int i = 0; i < INSTR_HASH_TABLE_SIZE; i++) {
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listInstr_[i].make_list(0);
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listInstr_[i].make_list(0);
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}
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}
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addIsaUserRV64I(pContext, listInstr_);
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addIsaUserRV64I();
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addIsaPrivilegedRV64I(pContext, listInstr_);
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addIsaPrivilegedRV64I();
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for (unsigned i = 0; i < listExtISA_.size(); i++) {
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for (unsigned i = 0; i < listExtISA_.size(); i++) {
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if (listExtISA_[i].to_string()[0] == 'A') {
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if (listExtISA_[i].to_string()[0] == 'A') {
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addIsaExtensionA(pContext, listInstr_);
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addIsaExtensionA();
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} else if (listExtISA_[i].to_string()[0] == 'C') {
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addIsaExtensionC();
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} else if (listExtISA_[i].to_string()[0] == 'F') {
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} else if (listExtISA_[i].to_string()[0] == 'F') {
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addIsaExtensionF(pContext, listInstr_);
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addIsaExtensionF();
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} else if (listExtISA_[i].to_string()[0] == 'M') {
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} else if (listExtISA_[i].to_string()[0] == 'M') {
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addIsaExtensionM(pContext, listInstr_);
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addIsaExtensionM();
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}
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}
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// Get global settings:
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const AttributeType *glb = RISCV_get_global_settings();
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if ((*glb)["SimEnable"].to_bool() && isEnable_.to_bool()) {
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if (!run()) {
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RISCV_error("Can't create thread.", NULL);
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return;
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}
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if (generateRegTraceFile_.to_bool()) {
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pContext->reg_trace_file = new std::ofstream("river_func_regs.log");
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}
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if (generateMemTraceFile_.to_bool()) {
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pContext->mem_trace_file = new std::ofstream("river_func_mem.log");
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}
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}
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}
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void CpuRiscV_Functional::hapTriggered(IFace *isrc, EHapType type,
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const char *descr) {
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RISCV_event_set(&config_done_);
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}
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void CpuRiscV_Functional::busyLoop() {
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RISCV_event_wait(&config_done_);
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while (isEnabled()) {
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updatePipeline();
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}
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}
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void CpuRiscV_Functional::updatePipeline() {
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IInstruction *instr;
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CpuContextType *pContext = getpContext();
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if (dport.valid) {
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dport.valid = 0;
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updateDebugPort();
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}
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}
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pContext->pc = pContext->npc;
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if (isRunning()) {
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fetchInstruction();
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}
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updateState();
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if (pContext->reset) {
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updateQueue();
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reset();
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return;
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}
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}
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instr = decodeInstruction(cacheline_);
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// Power-on
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if (isRunning()) {
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reset(false);
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last_hit_breakpoint_ = ~0;
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if (instr) {
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executeInstruction(instr, cacheline_);
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} else {
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pContext->npc += 4;
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generateException(EXCEPTION_InstrIllegal, pContext);
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RISCV_info("[%" RV_PRI64 "d] pc:%08x: %08x \t illegal instruction",
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CpuGeneric::postinitService();
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getStepCounter(),
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static_cast<uint32_t>(pContext->pc), cacheline_[0]);
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}
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}
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}
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updateQueue();
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unsigned CpuRiver_Functional::addSupportedInstruction(
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RiscvInstruction *instr) {
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handleTrap();
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AttributeType tmp(instr);
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}
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listInstr_[instr->hash()].add_to_list(&tmp);
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return 0;
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void CpuRiscV_Functional::updateState() {
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CpuContextType *pContext = getpContext();
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bool upd = true;
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switch (dbg_state_) {
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case STATE_Halted:
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upd = false;
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break;
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case STATE_Stepping:
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if (dbg_step_cnt_ <= pContext->step_cnt) {
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halt("Stepping breakpoint");
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upd = false;
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}
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break;
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default:;
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}
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if (upd) {
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pContext->step_cnt++;
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}
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}
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void CpuRiscV_Functional::updateQueue() {
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IFace *cb;
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CpuContextType *pContext = getpContext();
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queue_.initProc();
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queue_.pushPreQueued();
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while ((cb = queue_.getNext(pContext->step_cnt)) != 0) {
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static_cast<IClockListener *>(cb)->stepCallback(pContext->step_cnt);
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}
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}
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}
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void CpuRiscV_Functional::handleTrap() {
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void CpuRiver_Functional::handleTrap() {
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CpuContextType *pContext = getpContext();
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csr_mstatus_type mstatus;
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csr_mstatus_type mstatus;
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csr_mcause_type mcause;
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csr_mcause_type mcause;
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mstatus.value = pContext->csr[CSR_mstatus];
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if (interrupt_pending_ == 0) {
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mcause.value = pContext->csr[CSR_mcause];
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if (pContext->exception == 0 && pContext->interrupt == 0) {
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return;
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return;
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}
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}
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if (pContext->interrupt &&
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mstatus.bits.MIE == 0 && pContext->cur_prv_level == PRV_M) {
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mstatus.value = portCSR_.read(CSR_mstatus).val;
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mcause.value = portCSR_.read(CSR_mcause).val;
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uint64_t exception_mask = (1ull << INTERRUPT_USoftware) - 1;
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if ((interrupt_pending_ & exception_mask) == 0 &&
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mstatus.bits.MIE == 0 && cur_prv_level == PRV_M) {
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return;
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return;
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}
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}
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if (mcause.value == EXCEPTION_Breakpoint
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if (mcause.value == EXCEPTION_Breakpoint) {
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&& pContext->br_ctrl.bits.trap_on_break == 0) {
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DsuMapType::udbg_type::debug_region_type::breakpoint_control_reg t1;
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pContext->exception = 0;
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t1.val = br_control_.getValue().val;
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pContext->npc = pContext->pc;
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if (t1.bits.trap_on_break == 0) {
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sw_breakpoint_ = true;
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interrupt_pending_ &= ~(1ull << EXCEPTION_Breakpoint);
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npc_.setValue(pc_.getValue());
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halt("EBREAK Breakpoint");
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halt("EBREAK Breakpoint");
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return;
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return;
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}
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}
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}
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pContext->interrupt = 0;
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pContext->exception = 0;
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// All traps handle via machine mode while CSR mdelegate
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// All traps handle via machine mode while CSR mdelegate
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// doesn't setup other.
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// doesn't setup other.
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// @todo delegating
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// @todo delegating
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mstatus.bits.MPP = pContext->cur_prv_level;
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mstatus.bits.MPP = cur_prv_level;
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mstatus.bits.MPIE = (mstatus.value >> pContext->cur_prv_level) & 0x1;
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mstatus.bits.MPIE = (mstatus.value >> cur_prv_level) & 0x1;
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mstatus.bits.MIE = 0;
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mstatus.bits.MIE = 0;
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pContext->cur_prv_level = PRV_M;
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cur_prv_level = PRV_M;
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pContext->csr[CSR_mstatus] = mstatus.value;
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portCSR_.write(CSR_mstatus, mstatus.value);
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uint64_t xepc = (pContext->cur_prv_level << 8) + 0x41;
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int xepc = static_cast<int>((cur_prv_level << 8) + 0x41);
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if (pContext->exception) {
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if (interrupt_pending_ & exception_mask) {
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pContext->csr[xepc] = pContext->pc;
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// Exception
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portCSR_.write(xepc, pc_.getValue().val);
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} else {
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} else {
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// Software interrupt handled after instruction was executed
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// Software interrupt handled after instruction was executed
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pContext->csr[xepc] = pContext->npc;
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portCSR_.write(xepc, npc_.getValue().val);
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}
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npc_.setValue(portCSR_.read(CSR_mtvec));
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interrupt_pending_ = 0;
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}
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}
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pContext->npc = pContext->csr[CSR_mtvec];
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pContext->exception = 0;
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void CpuRiver_Functional::reset(bool active) {
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CpuGeneric::reset(active);
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portRegs_.reset();
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portCSR_.reset();
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portCSR_.write(CSR_mvendorid, vendorID_.to_uint64());
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portCSR_.write(CSR_mtvec, vectorTable_.to_uint64());
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cur_prv_level = PRV_M; // Current privilege level
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}
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}
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bool CpuRiscV_Functional::isRunning() {
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GenericInstruction *CpuRiver_Functional::decodeInstruction(Reg64Type *cache) {
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return (dbg_state_ != STATE_Halted);
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RiscvInstruction *instr = NULL;
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}
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int hash_idx = hash32(cacheline_[0].buf32[0]);
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for (unsigned i = 0; i < listInstr_[hash_idx].size(); i++) {
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void CpuRiscV_Functional::reset() {
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instr = static_cast<RiscvInstruction *>(
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CpuContextType *pContext = getpContext();
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listInstr_[hash_idx][i].to_iface());
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pContext->regs[0] = 0;
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if (instr->parse(cacheline_[0].buf32)) {
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pContext->pc = resetVector_.to_uint64();
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break;
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pContext->npc = resetVector_.to_uint64();
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pContext->exception = 0;
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pContext->interrupt = 0;
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pContext->interrupt_pending = 0;
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pContext->csr[CSR_mvendorid] = 0x0001; // UC Berkeley Rocket repo
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pContext->csr[CSR_mhartid] = 0;
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pContext->csr[CSR_marchid] = 0;
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pContext->csr[CSR_mimplementationid] = 0;
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pContext->csr[CSR_mtvec] = 0x100; // Hardwired RO value
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pContext->csr[CSR_mip] = 0; // clear pending interrupts
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pContext->csr[CSR_mie] = 0; // disabling interrupts
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pContext->csr[CSR_mepc] = 0;
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pContext->csr[CSR_mcause] = 0;
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pContext->csr[CSR_medeleg] = 0;
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pContext->csr[CSR_mideleg] = 0;
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pContext->csr[CSR_mtime] = 0;
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pContext->csr[CSR_mtimecmp] = 0;
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pContext->csr[CSR_uepc] = 0;
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pContext->csr[CSR_sepc] = 0;
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pContext->csr[CSR_hepc] = 0;
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csr_mstatus_type mstat;
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mstat.value = 0;
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pContext->csr[CSR_mstatus] = mstat.value;
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pContext->cur_prv_level = PRV_M; // Current privilege level
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pContext->step_cnt = 0;
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pContext->br_ctrl.val = 0;
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pContext->br_inject_fetch = false;
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pContext->br_status_ena = false;
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pContext->stack_trace_cnt = 0;
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}
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void CpuRiscV_Functional::fetchInstruction() {
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CpuContextType *pContext = getpContext();
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if (pContext->br_inject_fetch
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&& pContext->pc == pContext->br_address_fetch) {
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pContext->br_inject_fetch = false;
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cacheline_[0] = pContext->br_instr_fetch;
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return;
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}
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}
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trans_.action = MemAction_Read;
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instr = NULL;
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trans_.addr = pContext->pc;
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trans_.xsize = 4;
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trans_.wstrb = 0;
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pContext->ibus->b_transport(&trans_);
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cacheline_[0] = trans_.rpayload.b32[0];
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}
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}
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// Check compressed instructions:
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IInstruction *CpuRiscV_Functional::decodeInstruction(uint32_t *rpayload) {
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if (instr == NULL) {
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IInstruction *instr = NULL;
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hash_idx = hash16(cacheline_[0].buf16[0]);
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int hash_idx = hash32(rpayload[0]);
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for (unsigned i = 0; i < listInstr_[hash_idx].size(); i++) {
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for (unsigned i = 0; i < listInstr_[hash_idx].size(); i++) {
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instr = static_cast<IInstruction *>(
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instr = static_cast<RiscvInstruction *>(
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listInstr_[hash_idx][i].to_iface());
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listInstr_[hash_idx][i].to_iface());
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if (instr->parse(rpayload)) {
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if (instr->parse(cacheline_[0].buf32)) {
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break;
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break;
|
}
|
}
|
instr = NULL;
|
instr = NULL;
|
}
|
}
|
|
}
|
return instr;
|
return instr;
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}
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}
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|
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void CpuRiscV_Functional::debugRegOutput(const char *marker,
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void CpuRiver_Functional::generateIllegalOpcode() {
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CpuContextType *pContext) {
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raiseSignal(EXCEPTION_InstrIllegal);
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RISCV_debug("%s[%" RV_PRI64 "d] %d %08x: "
|
RISCV_error("Illegal instruction at 0x%08" RV_PRI64 "x", getPC());
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"1:%016" RV_PRI64 "x; 2:%016" RV_PRI64 "x; 3:%016" RV_PRI64 "x; 4:%016" RV_PRI64 "x "
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"5:%016" RV_PRI64 "x; 6:%016" RV_PRI64 "x; 7:%016" RV_PRI64 "x; 8:%016" RV_PRI64 "x "
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"9:%016" RV_PRI64 "x; 10:%016" RV_PRI64 "x; 11:%016" RV_PRI64 "x; 12:%016" RV_PRI64 "x "
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"13:%016" RV_PRI64 "x; 14:%016" RV_PRI64 "x; 15:%016" RV_PRI64 "x; 16:%016" RV_PRI64 "x "
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"17:%016" RV_PRI64 "x; 18:%016" RV_PRI64 "x; 19:%016" RV_PRI64 "x; 20:%016" RV_PRI64 "x "
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"21:%016" RV_PRI64 "x; 22:%016" RV_PRI64 "x; 24:%016" RV_PRI64 "x; 25:%016" RV_PRI64 "x "
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"25:%016" RV_PRI64 "x; 26:%016" RV_PRI64 "x; 27:%016" RV_PRI64 "x; 28:%016" RV_PRI64 "x "
|
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"29:%016" RV_PRI64 "x; 30:%016" RV_PRI64 "x; 31:%016" RV_PRI64 "x",
|
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marker,
|
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getStepCounter(),
|
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(int)pContext->cur_prv_level,
|
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(uint32_t)pContext->csr[CSR_mepc],
|
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pContext->regs[1], pContext->regs[2], pContext->regs[3], pContext->regs[4],
|
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pContext->regs[5], pContext->regs[6], pContext->regs[7], pContext->regs[8],
|
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pContext->regs[9], pContext->regs[10], pContext->regs[11], pContext->regs[12],
|
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pContext->regs[13], pContext->regs[14], pContext->regs[15], pContext->regs[16],
|
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pContext->regs[17], pContext->regs[18], pContext->regs[19], pContext->regs[20],
|
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pContext->regs[21], pContext->regs[22], pContext->regs[23], pContext->regs[24],
|
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pContext->regs[25], pContext->regs[26], pContext->regs[27], pContext->regs[28],
|
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pContext->regs[29], pContext->regs[30], pContext->regs[31]);
|
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}
|
}
|
|
|
void CpuRiscV_Functional::executeInstruction(IInstruction *instr,
|
void CpuRiver_Functional::trackContextStart() {
|
uint32_t *rpayload) {
|
if (reg_trace_file == 0) {
|
|
return;
|
CpuContextType *pContext = getpContext();
|
|
if (pContext->reg_trace_file) {
|
|
/** Save previous reg values to find modification after exec() */
|
|
for (int i = 0; i < Reg_Total; i++) {
|
|
iregs_prev[i] = pContext->regs[i];
|
|
}
|
}
|
|
/** Save previous reg values to find modification after exec() */
|
|
uint64_t *dst = portSavedRegs_.getpR64();
|
|
uint64_t *src = portRegs_.getpR64();
|
|
memcpy(dst, src, Reg_Total*sizeof(uint64_t));
|
}
|
}
|
|
|
instr->exec(cacheline_, pContext);
|
void CpuRiver_Functional::trackContextEnd() {
|
#if 0
|
if (reg_trace_file == 0) {
|
if (pContext->pc == 0x10000148 && pContext->regs[Reg_a0] != 3) {
|
return;
|
RISCV_debug("IstWrapper [%" RV_PRI64 "d]: idx=%" RV_PRI64 "d",
|
|
getStepCounter(), pContext->regs[Reg_a0]);
|
|
}
|
|
if (pContext->pc == 0x1000246c) {
|
|
RISCV_debug("new_thread [%" RV_PRI64 "d]: "
|
|
"Stack:%016" RV_PRI64 "x; StackSize:%" RV_PRI64 "d; Entry:%08" RV_PRI64 "x "
|
|
"tp:%016" RV_PRI64 "x => %016" RV_PRI64 "x; prio=%" RV_PRI64 "d",
|
|
getStepCounter(),
|
|
pContext->regs[Reg_a0], pContext->regs[Reg_a1], pContext->regs[Reg_a2],
|
|
pContext->regs[Reg_tp], pContext->regs[Reg_a0]+96,
|
|
pContext->regs[Reg_a6]);
|
|
}
|
}
|
#endif
|
|
if (pContext->reg_trace_file) {
|
|
int sz;
|
int sz;
|
sz = RISCV_sprintf(tstr, sizeof(tstr),"%8I64d [%08x] %08x: ",
|
char tstr[1024];
|
pContext->step_cnt, static_cast<uint32_t>(pContext->pc), rpayload[0]);
|
sz = RISCV_sprintf(tstr, sizeof(tstr),"%8I64d [%08x]: ",
|
|
step_cnt_, pc_.getValue().buf32[0]);
|
|
|
bool reg_changed = false;
|
bool reg_changed = false;
|
for (int i = 0; i < 32; i++) {
|
uint64_t *prev = portSavedRegs_.getpR64();
|
if (iregs_prev[i] != pContext->regs[i]) {
|
uint64_t *cur = portRegs_.getpR64();
|
|
for (int i = 0; i < Reg_Total; i++) {
|
|
if (prev[i] != cur[i]) {
|
reg_changed = true;
|
reg_changed = true;
|
sz += RISCV_sprintf(&tstr[sz], sizeof(tstr) - sz,
|
sz += RISCV_sprintf(&tstr[sz], sizeof(tstr) - sz,
|
"%3s <= %016I64x\n", IREGS_NAMES[i], pContext->regs[i]);
|
"%3s <= %016I64x",
|
}
|
IREGS_NAMES[i], cur[i]);//, instr_->name());
|
}
|
}
|
if (!reg_changed) {
|
|
sz += RISCV_sprintf(&tstr[sz], sizeof(tstr) - sz, "%s", "-\n");
|
|
}
|
}
|
(*pContext->reg_trace_file) << tstr;
|
if (instr_ && !reg_changed) {
|
pContext->reg_trace_file->flush();
|
sz += RISCV_sprintf(&tstr[sz], sizeof(tstr) - sz, "-", NULL);
|
}
|
|
|
|
if (generateRegTraceFile_.to_bool()) {
|
|
char msg[16];
|
|
int msg_len = 0;
|
|
IService *uart = NULL;
|
|
switch (pContext->step_cnt) {
|
|
case 22080:
|
|
uart = static_cast<IService *>(RISCV_get_service("uart0"));
|
|
msg[0] = 'h';
|
|
msg_len = 1;
|
|
break;
|
|
case 22500:
|
|
uart = static_cast<IService *>(RISCV_get_service("uart0"));
|
|
msg[0] = 'e';
|
|
msg[1] = 'l';
|
|
msg_len = 2;
|
|
break;
|
|
case 24350:
|
|
uart = static_cast<IService *>(RISCV_get_service("uart0"));
|
|
msg[0] = 'p';
|
|
msg[1] = '\r';
|
|
msg[2] = '\n';
|
|
msg_len = 3;
|
|
break;
|
|
default:;
|
|
}
|
}
|
|
(*reg_trace_file) << tstr << "\n";
|
if (uart) {
|
reg_trace_file->flush();
|
ISerial *iserial = static_cast<ISerial *>(
|
}
|
uart->getInterface(IFACE_SERIAL));
|
|
//iserial->writeData("pnp\r\n", 6);
|
void CpuRiver_Functional::raiseSignal(int idx) {
|
//iserial->writeData("highticks\r\n", 11);
|
if (idx < INTERRUPT_USoftware) {
|
iserial->writeData(msg, msg_len);
|
// Exception:
|
|
csr_mcause_type cause;
|
|
cause.value = 0;
|
|
cause.bits.irq = 0;
|
|
cause.bits.code = idx;
|
|
portCSR_.write(CSR_mcause, cause.value);
|
|
interrupt_pending_ |= 1LL << idx;
|
|
} else if (idx < SIGNAL_HardReset) {
|
|
csr_mcause_type cause;
|
|
cause.value = 0;
|
|
cause.bits.irq = 1;
|
|
cause.bits.code = idx - INTERRUPT_USoftware;
|
|
portCSR_.write(CSR_mcause, cause.value);
|
|
interrupt_pending_ |= 1LL << idx;
|
|
} else if (idx == SIGNAL_HardReset) {
|
|
} else {
|
|
RISCV_error("Raise unsupported signal %d", idx);
|
}
|
}
|
}
|
}
|
|
|
|
void CpuRiver_Functional::lowerSignal(int idx) {
|
if (pContext->regs[0] != 0) {
|
if (idx == SIGNAL_HardReset) {
|
RISCV_error("Register x0 was modificated (not equal to zero)", NULL);
|
} else if (idx < SIGNAL_HardReset) {
|
|
interrupt_pending_ &= ~(1 << idx);
|
|
} else {
|
|
RISCV_error("Lower unsupported signal %d", idx);
|
}
|
}
|
}
|
}
|
|
|
void CpuRiscV_Functional::registerStepCallback(IClockListener *cb,
|
uint64_t CpuRiver_Functional::readCSR(int idx) {
|
uint64_t t) {
|
if (idx == CSR_mtime) {
|
if (!isEnabled()) {
|
return step_cnt_;
|
if (t <= getpContext()->step_cnt) {
|
|
cb->stepCallback(t);
|
|
}
|
}
|
return;
|
return portCSR_.read(idx).val;
|
}
|
}
|
queue_.put(t, cb);
|
|
}
|
|
|
|
|
|
/**
|
|
* prv-1.9.1 page 29
|
|
*
|
|
* An interrupt i will be taken if bit i is set in both mip and mie,
|
|
* and if interrupts are globally enabled. By default, M-mode interrupts
|
|
* are globally enabled if the hart’s current privilege mode is less than M,
|
|
* or if the current privilege mode is M and the MIE bit in the mstatus
|
|
* register is set.
|
|
* If bit i in mideleg is set, however, interrupts are considered to be
|
|
* globally enabled if the hart’s current privilege mode equals the delegated
|
|
* privilege mode (H, S, or U) and that mode’s interrupt enable bit
|
|
* (HIE, SIE or UIE in mstatus) is set, or if the current privilege mode is
|
|
* less than the delegated privilege mode.
|
|
*/
|
|
void CpuRiscV_Functional::raiseSignal(int idx) {
|
|
CpuContextType *pContext = getpContext();
|
|
csr_mstatus_type mstatus;
|
|
mstatus.value = pContext->csr[CSR_mstatus];
|
|
|
|
|
void CpuRiver_Functional::writeCSR(int idx, uint64_t val) {
|
switch (idx) {
|
switch (idx) {
|
case CPU_SIGNAL_RESET:
|
// Read-Only registers
|
pContext->reset = true; // Active HIGH
|
case CSR_misa:
|
break;
|
case CSR_mvendorid:
|
case CPU_SIGNAL_EXT_IRQ:
|
case CSR_marchid:
|
if (pContext->reset) {
|
case CSR_mimplementationid:
|
|
case CSR_mhartid:
|
break;
|
break;
|
}
|
case CSR_mtime:
|
// External Interrupt controller pending bit
|
|
pContext->interrupt_pending |= (1ull << idx);
|
|
if (mstatus.bits.MIE == 0 && pContext->cur_prv_level == PRV_M) {
|
|
break;
|
|
}
|
|
/// @todo delegate interrupt to non-machine privilege level.
|
|
generateInterrupt(INTERRUPT_MExternal, pContext);
|
|
break;
|
break;
|
default:
|
default:
|
RISCV_error("Unsupported signalRaise(%d)", idx);
|
portCSR_.write(idx, val);
|
}
|
|
}
|
|
|
|
void CpuRiscV_Functional::lowerSignal(int idx) {
|
|
CpuContextType *pContext = getpContext();
|
|
switch (idx) {
|
|
case CPU_SIGNAL_RESET:
|
|
pContext->reset = false; // Active HIGH
|
|
break;
|
|
case CPU_SIGNAL_EXT_IRQ:
|
|
pContext->interrupt_pending &= ~(1 << idx);
|
|
break;
|
|
default:
|
|
RISCV_error("Unsupported lowerSignal(%d)", idx);
|
|
}
|
|
}
|
|
|
|
void CpuRiscV_Functional::updateDebugPort() {
|
|
CpuContextType *pContext = getpContext();
|
|
DsuMapType::udbg_type::debug_region_type::control_reg ctrl;
|
|
DebugPortTransactionType *trans = dport.trans;
|
|
trans->rdata = 0;
|
|
switch (trans->region) {
|
|
case 0: // CSR
|
|
trans->rdata = pContext->csr[trans->addr];
|
|
if (trans->write) {
|
|
pContext->csr[trans->addr] = trans->wdata;
|
|
}
|
|
break;
|
|
case 1: // IRegs
|
|
if (trans->addr < Reg_Total) {
|
|
trans->rdata = pContext->regs[trans->addr];
|
|
if (trans->write) {
|
|
pContext->regs[trans->addr] = trans->wdata;
|
|
}
|
|
} else if (trans->addr == Reg_Total) {
|
|
/** Read only register */
|
|
trans->rdata = pContext->pc;
|
|
} else if (trans->addr == (Reg_Total + 1)) {
|
|
trans->rdata = pContext->npc;
|
|
if (trans->write) {
|
|
pContext->npc = trans->wdata;
|
|
}
|
|
} else if (trans->addr == (Reg_Total + 2)) {
|
|
trans->rdata = pContext->stack_trace_cnt;
|
|
if (trans->write) {
|
|
pContext->stack_trace_cnt = static_cast<int>(trans->wdata);
|
|
}
|
|
} else if (trans->addr >= 128 &&
|
|
trans->addr < (128 + STACK_TRACE_BUF_SIZE)) {
|
|
trans->rdata = pContext->stack_trace_buf[trans->addr - 128];
|
|
}
|
|
break;
|
|
case 2: // Control
|
|
switch (trans->addr) {
|
|
case 0:
|
|
ctrl.val = trans->wdata;
|
|
if (trans->write) {
|
|
if (ctrl.bits.halt) {
|
|
halt();
|
|
} else if (ctrl.bits.stepping) {
|
|
step(dport.stepping_mode_steps);
|
|
} else {
|
|
go();
|
|
}
|
|
} else {
|
|
ctrl.val = 0;
|
|
ctrl.bits.halt = isHalt() ? 1: 0;
|
|
if (pContext->br_status_ena) {
|
|
ctrl.bits.breakpoint = 1;
|
|
}
|
|
ctrl.bits.core_id = 0;
|
|
}
|
|
trans->rdata = ctrl.val;
|
|
break;
|
|
case 1:
|
|
trans->rdata = dport.stepping_mode_steps;
|
|
if (trans->write) {
|
|
dport.stepping_mode_steps = trans->wdata;
|
|
}
|
|
break;
|
|
case 2:
|
|
trans->rdata = pContext->step_cnt;
|
|
break;
|
|
case 3:
|
|
trans->rdata = pContext->step_cnt;
|
|
break;
|
|
case 4:
|
|
trans->rdata = pContext->br_ctrl.val;
|
|
if (trans->write) {
|
|
pContext->br_ctrl.val = trans->wdata;
|
|
}
|
}
|
break;
|
|
case 5:
|
|
if (trans->write) {
|
|
addBreakpoint(trans->wdata);
|
|
}
|
|
break;
|
|
case 6:
|
|
if (trans->write) {
|
|
removeBreakpoint(trans->wdata);
|
|
}
|
|
break;
|
|
case 7:
|
|
trans->rdata = pContext->br_address_fetch;
|
|
if (trans->write) {
|
|
pContext->br_address_fetch = trans->wdata;
|
|
}
|
|
break;
|
|
case 8:
|
|
trans->rdata = pContext->br_instr_fetch;
|
|
if (trans->write) {
|
|
pContext->br_inject_fetch = true;
|
|
pContext->br_status_ena = false;
|
|
pContext->br_instr_fetch = static_cast<uint32_t>(trans->wdata);
|
|
}
|
|
break;
|
|
default:;
|
|
}
|
|
break;
|
|
default:;
|
|
}
|
|
dport.cb->nb_response_debug_port(dport.trans);
|
|
}
|
|
|
|
void
|
|
CpuRiscV_Functional::nb_transport_debug_port(DebugPortTransactionType *trans,
|
|
IDbgNbResponse *cb) {
|
|
dport.trans = trans;
|
|
dport.cb = cb;
|
|
dport.valid = true;
|
|
}
|
|
|
|
void CpuRiscV_Functional::halt(const char *descr) {
|
|
CpuContextType *pContext = getpContext();
|
|
dbg_state_ = STATE_Halted;
|
|
|
|
if (descr == NULL) {
|
|
RISCV_printf0(
|
|
"[%" RV_PRI64 "d] pc:%016" RV_PRI64 "x: %08x \t CPU halted",
|
|
getStepCounter(), pContext->pc, cacheline_[0]);
|
|
} else {
|
|
RISCV_printf0("[%" RV_PRI64 "d] pc:%016" RV_PRI64 "x: %08x \t %s",
|
|
getStepCounter(), pContext->pc, cacheline_[0], descr);
|
|
}
|
|
}
|
|
|
|
void CpuRiscV_Functional::go() {
|
|
dbg_state_ = STATE_Normal;
|
|
}
|
|
|
|
void CpuRiscV_Functional::step(uint64_t cnt) {
|
|
CpuContextType *pContext = getpContext();
|
|
dbg_step_cnt_ = pContext->step_cnt + cnt;
|
|
dbg_state_ = STATE_Stepping;
|
|
}
|
|
|
|
uint64_t CpuRiscV_Functional::getReg(uint64_t idx) {
|
|
CpuContextType *pContext = getpContext();
|
|
if (idx >= 0 && idx < 32) {
|
|
return pContext->regs[idx];
|
|
}
|
|
return REG_INVALID;
|
|
}
|
|
|
|
void CpuRiscV_Functional::setReg(uint64_t idx, uint64_t val) {
|
|
CpuContextType *pContext = getpContext();
|
|
if (idx >= 0 && idx < 32) {
|
|
pContext->regs[idx] = val;
|
|
}
|
|
}
|
|
|
|
uint64_t CpuRiscV_Functional::getPC() {
|
|
CpuContextType *pContext = getpContext();
|
|
return pContext->pc;
|
|
}
|
|
|
|
void CpuRiscV_Functional::setPC(uint64_t val) {
|
|
CpuContextType *pContext = getpContext();
|
|
pContext->pc = val;
|
|
}
|
|
|
|
uint64_t CpuRiscV_Functional::getNPC() {
|
|
CpuContextType *pContext = getpContext();
|
|
return pContext->npc;
|
|
}
|
|
|
|
void CpuRiscV_Functional::setNPC(uint64_t val) {
|
|
CpuContextType *pContext = getpContext();
|
|
pContext->npc = val;
|
|
}
|
|
|
|
void CpuRiscV_Functional::addBreakpoint(uint64_t addr) {
|
|
//CpuContextType *pContext = getpContext();
|
|
}
|
|
|
|
void CpuRiscV_Functional::removeBreakpoint(uint64_t addr) {
|
|
//CpuContextType *pContext = getpContext();
|
|
}
|
|
|
|
void CpuRiscV_Functional::hitBreakpoint(uint64_t addr) {
|
|
CpuContextType *pContext = getpContext();
|
|
if (addr == last_hit_breakpoint_) {
|
|
return;
|
|
}
|
|
dbg_state_ = STATE_Halted;
|
|
last_hit_breakpoint_ = addr;
|
|
|
|
RISCV_printf0("[%" RV_PRI64 "d] pc:%016" RV_PRI64 "x: %08x \t stop on breakpoint",
|
|
getStepCounter(), pContext->pc, cacheline_[0]);
|
|
}
|
}
|
|
|
} // namespace debugger
|
} // namespace debugger
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
