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*/
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*/
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#ifndef __DEBUGGER_CPU_RISCV_FUNCTIONAL_H__
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#ifndef __DEBUGGER_CPU_RISCV_FUNCTIONAL_H__
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#define __DEBUGGER_CPU_RISCV_FUNCTIONAL_H__
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#define __DEBUGGER_CPU_RISCV_FUNCTIONAL_H__
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#include "iclass.h"
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#include <riscv-isa.h>
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#include "iservice.h"
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#include "ihap.h"
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#include "async_tqueue.h"
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#include "coreservices/ithread.h"
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#include "coreservices/icpuriscv.h"
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#include "coreservices/imemop.h"
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#include "coreservices/iclock.h"
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#include "coreservices/iclklistener.h"
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#include "instructions.h"
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#include "instructions.h"
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#include "generic/cpu_generic.h"
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#include "coreservices/icpuriscv.h"
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#include "coreservices/isocinfo.h"
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namespace debugger {
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namespace debugger {
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class CpuRiscV_Functional : public IService,
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class CpuRiver_Functional : public CpuGeneric,
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public IThread,
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public ICpuRiscV {
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public ICpuRiscV,
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public IClock,
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public IHap {
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public:
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public:
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CpuRiscV_Functional(const char *name);
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explicit CpuRiver_Functional(const char *name);
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virtual ~CpuRiscV_Functional();
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virtual ~CpuRiver_Functional();
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/** IService interface */
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/** IService interface */
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virtual void postinitService();
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virtual void postinitService();
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/** ICpuRiscV interface */
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/** IResetListener itnterface */
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virtual void reset(bool active);
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/** ICpuGeneric interface */
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virtual void raiseSignal(int idx);
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virtual void raiseSignal(int idx);
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virtual void lowerSignal(int idx);
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virtual void lowerSignal(int idx);
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virtual void nb_transport_debug_port(DebugPortTransactionType *trans,
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virtual void raiseSoftwareIrq() {}
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IDbgNbResponse *cb);
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virtual uint64_t getIrqAddress(int idx) { return readCSR(CSR_mtvec); }
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/** IClock */
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// Common River methods shared with instructions:
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virtual uint64_t getStepCounter() { return cpu_context_.step_cnt; }
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uint64_t *getpRegs() { return portRegs_.getpR64(); }
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virtual void registerStepCallback(IClockListener *cb, uint64_t t);
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uint64_t readCSR(int idx);
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void writeCSR(int idx, uint64_t val);
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/** IHap */
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virtual void hapTriggered(IFace *isrc, EHapType type, const char *descr);
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protected:
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protected:
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/** IThread interface */
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/** CpuGeneric common methods */
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virtual void busyLoop();
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virtual EEndianessType endianess() { return LittleEndian; }
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virtual GenericInstruction *decodeInstruction(Reg64Type *cache);
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private:
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virtual void generateIllegalOpcode();
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bool isHalt() { return dbg_state_ == STATE_Halted; }
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virtual void handleTrap();
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void halt(const char *descr=NULL);
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/** Tack Registers changes during execution */
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void go();
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virtual void trackContextStart();
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void step(uint64_t cnt);
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/** // Stop tracking and write trace file */
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uint64_t getReg(uint64_t idx);
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virtual void trackContextEnd();
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void setReg(uint64_t idx, uint64_t val);
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uint64_t getPC();
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void addIsaUserRV64I();
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void setPC(uint64_t val);
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void addIsaPrivilegedRV64I();
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uint64_t getNPC();
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void addIsaExtensionA();
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void setNPC(uint64_t val);
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void addIsaExtensionC();
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void addBreakpoint(uint64_t addr);
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void addIsaExtensionF();
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void removeBreakpoint(uint64_t addr);
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void addIsaExtensionM();
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void hitBreakpoint(uint64_t addr);
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unsigned addSupportedInstruction(RiscvInstruction *instr);
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CpuContextType *getpContext() { return &cpu_context_; }
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uint32_t hash32(uint32_t val) { return (val >> 2) & 0x1f; }
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uint32_t hash32(uint32_t val) { return (val >> 2) & 0x1f; }
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/** Compressed instruction */
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void updatePipeline();
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uint32_t hash16(uint16_t val) {
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void updateState();
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uint32_t t1 = val & 0x3;
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void updateDebugPort();
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return 0x20 | ((val >> 13) << 2) | t1;
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void updateQueue();
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}
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bool isRunning();
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void reset();
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void handleTrap();
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void fetchInstruction();
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IInstruction *decodeInstruction(uint32_t *rpayload);
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void executeInstruction(IInstruction *instr, uint32_t *rpayload);
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void debugRegOutput(const char *marker, CpuContextType *pContext);
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private:
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private:
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static const int INSTR_HASH_TABLE_SIZE = 1 << 5;
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AttributeType isEnable_;
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AttributeType bus_;
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AttributeType listExtISA_;
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AttributeType listExtISA_;
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AttributeType freqHz_;
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AttributeType vendorID_;
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AttributeType generateRegTraceFile_;
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AttributeType vectorTable_;
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AttributeType generateMemTraceFile_;
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AttributeType resetVector_;
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event_def config_done_;
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AsyncTQueueType queue_;
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uint64_t last_hit_breakpoint_;
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Axi4TransactionType trans_;
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uint32_t cacheline_[512/4];
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// Registers:
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static const int INSTR_HASH_TABLE_SIZE = 1 << 6;
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AttributeType listInstr_[INSTR_HASH_TABLE_SIZE];
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AttributeType listInstr_[INSTR_HASH_TABLE_SIZE];
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CpuContextType cpu_context_;
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enum EDebugState {
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GenericReg64Bank portRegs_;
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STATE_Halted,
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GenericReg64Bank portSavedRegs_;
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STATE_Normal,
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GenericReg64Bank portCSR_;
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STATE_Stepping
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} dbg_state_;
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uint64_t dbg_step_cnt_;
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char tstr[1024];
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uint64_t iregs_prev[32]; // to detect changes
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struct DebugPortType {
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bool valid;
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DebugPortTransactionType *trans;
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IDbgNbResponse *cb;
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// local registers
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uint64_t stepping_mode_steps;
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} dport;
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};
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};
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DECLARE_CLASS(CpuRiscV_Functional)
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DECLARE_CLASS(CpuRiver_Functional)
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} // namespace debugger
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} // namespace debugger
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#endif // __DEBUGGER_CPU_RISCV_FUNCTIONAL_H__
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#endif // __DEBUGGER_CPU_RISCV_FUNCTIONAL_H__
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