| Line 1... |
Line 1... |
/**
|
/**
|
* @file
|
* @file
|
* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
|
* @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
|
* @author Sergey Khabarov - sergeykhbr@gmail.com
|
* @author Sergey Khabarov - sergeykhbr@gmail.com
|
* @brief Instruction object declaration.
|
* @brief Instruction object declaration.
|
*/
|
*/
|
|
|
#ifndef __DEBUGGER_CPU_RISCV_INSTRUCTIONS_H__
|
#ifndef __DEBUGGER_CPU_RISCV_INSTRUCTIONS_H__
|
#define __DEBUGGER_CPU_RISCV_INSTRUCTIONS_H__
|
#define __DEBUGGER_CPU_RISCV_INSTRUCTIONS_H__
|
|
|
#include <inttypes.h>
|
#include <inttypes.h>
|
#include "iface.h"
|
#include "generic/cpu_generic.h"
|
#include "attribute.h"
|
|
#include "iinstr.h"
|
|
|
|
namespace debugger {
|
namespace debugger {
|
|
|
class IsaProcessor : public IInstruction {
|
class CpuRiver_Functional;
|
|
|
|
class RiscvInstruction : public GenericInstruction {
|
public:
|
public:
|
IsaProcessor(const char *name, const char *bits) {
|
RiscvInstruction(CpuRiver_Functional *icpu, const char *name,
|
name_ = name;
|
const char *bits);
|
mask_ = 0;
|
|
opcode_ = 0;
|
|
for (int i = 0; i < 32; i++) {
|
|
switch (bits[i]) {
|
|
case '0':
|
|
break;
|
|
case '1':
|
|
opcode_ |= (1 << (31 - i));
|
|
break;
|
|
case '?':
|
|
mask_ |= (1 << (31 - i));
|
|
break;
|
|
default:;
|
|
}
|
|
}
|
|
mask_ ^= ~0;
|
|
}
|
|
|
|
// IInstruction interface:
|
// IInstruction interface:
|
virtual const char *name() { return name_; }
|
virtual const char *name() { return name_.to_string(); }
|
|
|
virtual bool parse(uint32_t *payload) {
|
virtual bool parse(uint32_t *payload) {
|
return ((payload[0] & mask_) == opcode_);
|
return ((payload[0] & mask_) == opcode_);
|
}
|
}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *regs) =0;
|
|
|
|
virtual uint32_t hash() {
|
virtual uint32_t hash() {
|
return (opcode_ >> 2) & 0x1F;
|
return (opcode_ >> 2) & 0x1F;
|
}
|
}
|
|
|
|
uint16_t hash16() {
|
|
uint16_t t1 = static_cast<uint16_t>(opcode_) & 0x3;
|
|
return 0x20 | ((static_cast<uint16_t>(opcode_) >> 13) << 2) | t1;
|
|
}
|
|
|
protected:
|
protected:
|
const char *name_;
|
AttributeType name_;
|
|
CpuRiver_Functional *icpu_;
|
uint32_t mask_;
|
uint32_t mask_;
|
uint32_t opcode_;
|
uint32_t opcode_;
|
|
uint64_t *R;
|
|
};
|
|
|
|
class RiscvInstruction16 : public RiscvInstruction {
|
|
public:
|
|
RiscvInstruction16(CpuRiver_Functional *icpu, const char *name,
|
|
const char *bits) : RiscvInstruction(icpu, name, bits) {}
|
|
|
|
// IInstruction interface:
|
|
virtual uint32_t hash() {
|
|
uint16_t t1 = static_cast<uint16_t>(opcode_) & 0x3;
|
|
return 0x20 | ((static_cast<uint16_t>(opcode_) >> 13) << 2) | t1;
|
|
}
|
};
|
};
|
|
|
unsigned addSupportedInstruction(IsaProcessor *instr, AttributeType *out);
|
|
|
|
} // namespace debugger
|
} // namespace debugger
|
|
|
#endif // __DEBUGGER_CPU_RISCV_INSTRUCTIONS_H__
|
#endif // __DEBUGGER_CPU_RISCV_INSTRUCTIONS_H__
|
|
|
No newline at end of file
|
No newline at end of file
|
