| Line 5... |
Line 5... |
* @brief RISC-V extension-M.
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* @brief RISC-V extension-M.
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*/
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*/
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|
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#include "api_utils.h"
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#include "api_utils.h"
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#include "riscv-isa.h"
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#include "riscv-isa.h"
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#include "instructions.h"
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#include "cpu_riscv_func.h"
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|
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namespace debugger {
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namespace debugger {
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|
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/**
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/**
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* @brief The DIV signed division
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* @brief The DIV signed division
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*/
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*/
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class DIV : public IsaProcessor {
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class DIV : public RiscvInstruction {
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public:
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public:
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DIV() : IsaProcessor("DIV", "0000001??????????100?????0110011") {}
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DIV(CpuRiver_Functional *icpu)
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: RiscvInstruction(icpu, "DIV", "0000001??????????100?????0110011") {}
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|
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virtual void exec(uint32_t *payload, CpuContextType *data) {
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virtual int exec(Reg64Type *payload) {
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ISA_R_type u;
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ISA_R_type u;
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u.value = payload[0];
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u.value = payload->buf32[0];
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if (data->regs[u.bits.rs2]) {
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if (R[u.bits.rs2]) {
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data->regs[u.bits.rd] = static_cast<int64_t>(data->regs[u.bits.rs1])
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R[u.bits.rd] = static_cast<int64_t>(R[u.bits.rs1])
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/ static_cast<int64_t>(data->regs[u.bits.rs2]);
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/ static_cast<int64_t>(R[u.bits.rs2]);
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} else {
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} else {
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data->regs[u.bits.rd] = 0;
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R[u.bits.rd] = 0;
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}
|
}
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data->npc = data->pc + 4;
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return 4;
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}
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}
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};
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};
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/**
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/**
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* @brief DIVU unsigned division
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* @brief DIVU unsigned division
|
*/
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*/
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class DIVU : public IsaProcessor {
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class DIVU : public RiscvInstruction {
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public:
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public:
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DIVU() : IsaProcessor("DIVU", "0000001??????????101?????0110011") {}
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DIVU(CpuRiver_Functional *icpu)
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: RiscvInstruction(icpu, "DIVU", "0000001??????????101?????0110011") {}
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virtual void exec(uint32_t *payload, CpuContextType *data) {
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virtual int exec(Reg64Type *payload) {
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ISA_R_type u;
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ISA_R_type u;
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u.value = payload[0];
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u.value = payload->buf32[0];
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if (data->regs[u.bits.rs2]) {
|
if (R[u.bits.rs2]) {
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data->regs[u.bits.rd] =
|
R[u.bits.rd] = R[u.bits.rs1] / R[u.bits.rs2];
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data->regs[u.bits.rs1] / data->regs[u.bits.rs2];
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} else {
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} else {
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data->regs[u.bits.rd] = 0;
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R[u.bits.rd] = 0;
|
}
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}
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data->npc = data->pc + 4;
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return 4;
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}
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}
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};
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};
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/**
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/**
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* @brief DIVUW 32-bits unsigned division (RV64I)
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* @brief DIVUW 32-bits unsigned division (RV64I)
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*/
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*/
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class DIVUW : public IsaProcessor {
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class DIVUW : public RiscvInstruction {
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public:
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public:
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DIVUW() : IsaProcessor("DIVUW", "0000001??????????101?????0111011") {}
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DIVUW(CpuRiver_Functional *icpu) :
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RiscvInstruction(icpu, "DIVUW", "0000001??????????101?????0111011") {}
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virtual void exec(uint32_t *payload, CpuContextType *data) {
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virtual int exec(Reg64Type *payload) {
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ISA_R_type u;
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ISA_R_type u;
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u.value = payload[0];
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u.value = payload->buf32[0];
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if (static_cast<uint32_t>(data->regs[u.bits.rs2])) {
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if (static_cast<uint32_t>(R[u.bits.rs2])) {
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data->regs[u.bits.rd] =
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R[u.bits.rd] =
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static_cast<uint32_t>(data->regs[u.bits.rs1]) /
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static_cast<uint32_t>(R[u.bits.rs1]) /
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static_cast<uint32_t>(data->regs[u.bits.rs2]);
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static_cast<uint32_t>(R[u.bits.rs2]);
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} else {
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} else {
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data->regs[u.bits.rd] = 0;
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R[u.bits.rd] = 0;
|
}
|
}
|
data->npc = data->pc + 4;
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return 4;
|
}
|
}
|
};
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};
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|
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/**
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/**
|
* @brief DIVW 32-bits signed division (RV64I)
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* @brief DIVW 32-bits signed division (RV64I)
|
*/
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*/
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class DIVW : public IsaProcessor {
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class DIVW : public RiscvInstruction {
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public:
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public:
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DIVW() : IsaProcessor("DIVW", "0000001??????????100?????0111011") {}
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DIVW(CpuRiver_Functional *icpu)
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: RiscvInstruction(icpu, "DIVW", "0000001??????????100?????0111011") {}
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virtual void exec(uint32_t *payload, CpuContextType *data) {
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virtual int exec(Reg64Type *payload) {
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ISA_R_type u;
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ISA_R_type u;
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u.value = payload[0];
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u.value = payload->buf32[0];
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int32_t divident = static_cast<int32_t>(data->regs[u.bits.rs1]);
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int32_t divident = static_cast<int32_t>(R[u.bits.rs1]);
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int32_t divisor = static_cast<int32_t>(data->regs[u.bits.rs2]);
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int32_t divisor = static_cast<int32_t>(R[u.bits.rs2]);
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if (divisor) {
|
if (divisor) {
|
data->regs[u.bits.rd] = static_cast<int64_t>(divident / divisor);
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R[u.bits.rd] = static_cast<int64_t>(divident / divisor);
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} else {
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} else {
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data->regs[u.bits.rd] = 0;
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R[u.bits.rd] = 0;
|
}
|
}
|
data->npc = data->pc + 4;
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return 4;
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}
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}
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};
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};
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/**
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/**
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* @brief The MUL signed multiplication
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* @brief The MUL signed multiplication
|
*
|
*
|
* MUL performs an XLEN-bit XLEN-bit multiplication and places the lower XLEN
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* MUL performs an XLEN-bit XLEN-bit multiplication and places the lower XLEN
|
* bits in the destination register.
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* bits in the destination register.
|
*/
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*/
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class MUL : public IsaProcessor {
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class MUL : public RiscvInstruction {
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public:
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public:
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MUL() : IsaProcessor("MUL", "0000001??????????000?????0110011") {}
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MUL(CpuRiver_Functional *icpu)
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: RiscvInstruction(icpu, "MUL", "0000001??????????000?????0110011") {}
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|
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virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
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ISA_R_type u;
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ISA_R_type u;
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u.value = payload[0];
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u.value = payload->buf32[0];
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data->regs[u.bits.rd] = static_cast<int64_t>(data->regs[u.bits.rs1])
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R[u.bits.rd] = static_cast<int64_t>(R[u.bits.rs1])
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* static_cast<int64_t>(data->regs[u.bits.rs2]);
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* static_cast<int64_t>(R[u.bits.rs2]);
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data->npc = data->pc + 4;
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return 4;
|
}
|
}
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};
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};
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|
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/**
|
/**
|
* @brief The MULW 32-bits signed multiplication (RV64I)
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* @brief The MULW 32-bits signed multiplication (RV64I)
|
| Line 119... |
Line 123... |
* registers, placing the sign-extension of the lower 32 bits of the result
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* registers, placing the sign-extension of the lower 32 bits of the result
|
* into the destination register. MUL can be used to obtain the upper 32 bits
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* into the destination register. MUL can be used to obtain the upper 32 bits
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* of the 64-bit product, but signed arguments must be proper 32-bit signed
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* of the 64-bit product, but signed arguments must be proper 32-bit signed
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* values, whereas unsigned arguments must have their upper 32 bits clear.
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* values, whereas unsigned arguments must have their upper 32 bits clear.
|
*/
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*/
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class MULW : public IsaProcessor {
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class MULW : public RiscvInstruction {
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public:
|
public:
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MULW() : IsaProcessor("MULW", "0000001??????????000?????0111011") {}
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MULW(CpuRiver_Functional *icpu)
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: RiscvInstruction(icpu, "MULW", "0000001??????????000?????0111011") {}
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|
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virtual void exec(uint32_t *payload, CpuContextType *data) {
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virtual int exec(Reg64Type *payload) {
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ISA_R_type u;
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ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
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int32_t m1 = static_cast<int32_t>(data->regs[u.bits.rs1]);
|
int32_t m1 = static_cast<int32_t>(R[u.bits.rs1]);
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int32_t m2 = static_cast<int32_t>(data->regs[u.bits.rs2]);
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int32_t m2 = static_cast<int32_t>(R[u.bits.rs2]);
|
|
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data->regs[u.bits.rd] = static_cast<int64_t>(m1 * m2);
|
R[u.bits.rd] = static_cast<int64_t>(m1 * m2);
|
if (data->regs[u.bits.rd] & (1LL << 31)) {
|
if (R[u.bits.rd] & (1LL << 31)) {
|
data->regs[u.bits.rd] |= EXT_SIGN_32;
|
R[u.bits.rd] |= EXT_SIGN_32;
|
}
|
}
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief The REM (remainder of the corresponding signed division operation)
|
* @brief The REM (remainder of the corresponding signed division operation)
|
*/
|
*/
|
class REM : public IsaProcessor {
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class REM : public RiscvInstruction {
|
public:
|
public:
|
REM() : IsaProcessor("REM", "0000001??????????110?????0110011") {}
|
REM(CpuRiver_Functional *icpu)
|
|
: RiscvInstruction(icpu, "REM", "0000001??????????110?????0110011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
data->regs[u.bits.rd] = static_cast<int64_t>(data->regs[u.bits.rs1])
|
R[u.bits.rd] = static_cast<int64_t>(R[u.bits.rs1])
|
% static_cast<int64_t>(data->regs[u.bits.rs2]);
|
% static_cast<int64_t>(R[u.bits.rs2]);
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief The REMU (remainder of the corresponding unsgined division operation)
|
* @brief The REMU (remainder of the corresponding unsgined division operation)
|
*/
|
*/
|
class REMU : public IsaProcessor {
|
class REMU : public RiscvInstruction {
|
public:
|
public:
|
REMU() : IsaProcessor("REMU", "0000001??????????111?????0110011") {}
|
REMU(CpuRiver_Functional *icpu)
|
|
: RiscvInstruction(icpu, "REMU", "0000001??????????111?????0110011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = R[u.bits.rs1] % R[u.bits.rs2];
|
data->regs[u.bits.rs1] % data->regs[u.bits.rs2];
|
return 4;
|
data->npc = data->pc + 4;
|
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief REMW signed reminder operation
|
* @brief REMW signed reminder operation
|
| Line 177... |
Line 183... |
* REMW and REMUW instructions are only valid
|
* REMW and REMUW instructions are only valid
|
* for RV64, and provide the corresponding signed and unsigned remainder
|
* for RV64, and provide the corresponding signed and unsigned remainder
|
* operations respectively.
|
* operations respectively.
|
* Both REMW and REMUW sign-extend the 32-bit result to 64 bits.
|
* Both REMW and REMUW sign-extend the 32-bit result to 64 bits.
|
*/
|
*/
|
class REMW : public IsaProcessor {
|
class REMW : public RiscvInstruction {
|
public:
|
public:
|
REMW() : IsaProcessor("REMW", "0000001??????????110?????0111011") {}
|
REMW(CpuRiver_Functional *icpu)
|
|
: RiscvInstruction(icpu, "REMW", "0000001??????????110?????0111011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
int32_t tmp;
|
int32_t tmp;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
tmp = static_cast<int32_t>(data->regs[u.bits.rs1])
|
tmp = static_cast<int32_t>(R[u.bits.rs1])
|
% static_cast<int32_t>(data->regs[u.bits.rs2]);
|
% static_cast<int32_t>(R[u.bits.rs2]);
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = static_cast<uint64_t>(static_cast<int64_t>(tmp));
|
static_cast<uint64_t>(static_cast<int64_t>(tmp));
|
return 4;
|
data->npc = data->pc + 4;
|
|
}
|
}
|
};
|
};
|
|
|
class REMUW : public IsaProcessor {
|
class REMUW : public RiscvInstruction {
|
public:
|
public:
|
REMUW() : IsaProcessor("REMUW", "0000001??????????111?????0111011") {}
|
REMUW(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "REMUW", "0000001??????????111?????0111011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
uint32_t tmp;
|
uint32_t tmp;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
tmp = static_cast<uint32_t>(data->regs[u.bits.rs1])
|
tmp = static_cast<uint32_t>(R[u.bits.rs1])
|
% static_cast<uint32_t>(data->regs[u.bits.rs2]);
|
% static_cast<uint32_t>(R[u.bits.rs2]);
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = static_cast<uint64_t>(static_cast<int64_t>(tmp));
|
static_cast<uint64_t>(static_cast<int64_t>(tmp));
|
return 4;
|
data->npc = data->pc + 4;
|
|
}
|
}
|
};
|
};
|
|
|
void addIsaExtensionM(CpuContextType *data, AttributeType *out) {
|
void CpuRiver_Functional::addIsaExtensionM() {
|
addSupportedInstruction(new DIV, out);
|
addSupportedInstruction(new DIV(this));
|
addSupportedInstruction(new DIVU, out);
|
addSupportedInstruction(new DIVU(this));
|
addSupportedInstruction(new DIVUW, out);
|
addSupportedInstruction(new DIVUW(this));
|
addSupportedInstruction(new DIVW, out);
|
addSupportedInstruction(new DIVW(this));
|
addSupportedInstruction(new MUL, out);
|
addSupportedInstruction(new MUL(this));
|
addSupportedInstruction(new MULW, out);
|
addSupportedInstruction(new MULW(this));
|
addSupportedInstruction(new REM, out);
|
addSupportedInstruction(new REM(this));
|
addSupportedInstruction(new REMU, out);
|
addSupportedInstruction(new REMU(this));
|
addSupportedInstruction(new REMW, out);
|
addSupportedInstruction(new REMW(this));
|
addSupportedInstruction(new REMUW, out);
|
addSupportedInstruction(new REMUW(this));
|
|
|
// TODO
|
// TODO
|
/*
|
/*
|
addInstr("MULH", "0000001??????????001?????0110011", NULL, out);
|
addInstr("MULH", "0000001??????????001?????0110011", NULL, out);
|
addInstr("MULHSU", "0000001??????????010?????0110011", NULL, out);
|
addInstr("MULHSU", "0000001??????????010?????0110011", NULL, out);
|
addInstr("MULHU", "0000001??????????011?????0110011", NULL, out);
|
addInstr("MULHU", "0000001??????????011?????0110011", NULL, out);
|
*/
|
*/
|
data->csr[CSR_misa] |= (1LL << ('M' - 'A'));
|
|
|
uint64_t isa = portCSR_.read(CSR_misa).val;
|
|
portCSR_.write(CSR_misa, isa | (1LL << ('M' - 'A')));
|
}
|
}
|
|
|
} // namespace debugger
|
} // namespace debugger
|
|
|
No newline at end of file
|
No newline at end of file
|
