| Line 5... |
Line 5... |
* @brief Base ISA implementation (extension I, user level).
|
* @brief Base ISA implementation (extension I, user level).
|
*/
|
*/
|
|
|
#include "api_utils.h"
|
#include "api_utils.h"
|
#include "riscv-isa.h"
|
#include "riscv-isa.h"
|
#include "instructions.h"
|
#include "cpu_riscv_func.h"
|
|
|
namespace debugger {
|
namespace debugger {
|
|
|
void generateException(uint64_t code, CpuContextType *data);
|
|
|
|
/**
|
/**
|
* @brief Addition. Overflows are ignored
|
* @brief Addition. Overflows are ignored
|
*/
|
*/
|
class ADD : public IsaProcessor {
|
class ADD : public RiscvInstruction {
|
public:
|
public:
|
ADD() : IsaProcessor("ADD", "0000000??????????000?????0110011") {}
|
ADD(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "ADD", "0000000??????????000?????0110011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = R[u.bits.rs1] + R[u.bits.rs2];
|
data->regs[u.bits.rs1] + data->regs[u.bits.rs2];
|
return 4;
|
data->npc = data->pc + 4;
|
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief Add immediate
|
* @brief Add immediate
|
| Line 35... |
Line 33... |
* ADDI adds the sign-extended 12-bit immediate to register rs1.
|
* ADDI adds the sign-extended 12-bit immediate to register rs1.
|
* Arithmetic overflow is ignored and the result is simply the low 32-bits of
|
* Arithmetic overflow is ignored and the result is simply the low 32-bits of
|
* the result. ADDI rd, rs1, 0 is used to implement the MV rd, rs1 assembler
|
* the result. ADDI rd, rs1, 0 is used to implement the MV rd, rs1 assembler
|
* pseudo-instruction.
|
* pseudo-instruction.
|
*/
|
*/
|
class ADDI : public IsaProcessor {
|
class ADDI : public RiscvInstruction {
|
public:
|
public:
|
ADDI() : IsaProcessor("ADDI", "?????????????????000?????0010011") {}
|
ADDI(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "ADDI", "?????????????????000?????0010011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
uint64_t imm = u.bits.imm;
|
uint64_t imm = u.bits.imm;
|
if (imm & 0x800) {
|
if (imm & 0x800) {
|
imm |= EXT_SIGN_12;
|
imm |= EXT_SIGN_12;
|
}
|
}
|
data->regs[u.bits.rd] = data->regs[u.bits.rs1] + imm;
|
R[u.bits.rd] = R[u.bits.rs1] + imm;
|
data->npc = data->pc + 4;
|
return 4;
|
|
|
if (u.bits.rs1 == 0) {
|
|
RISCV_sprintf(data->disasm, sizeof(data->disasm),
|
|
"li %s,%d", IREGS_NAMES[u.bits.rd], static_cast<uint32_t>(imm));
|
|
} else {
|
|
RISCV_sprintf(data->disasm, sizeof(data->disasm),
|
|
"addi %s,%s,%d", IREGS_NAMES[u.bits.rd],
|
|
IREGS_NAMES[u.bits.rs1],
|
|
static_cast<uint32_t>(imm));
|
|
}
|
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief Add immediate with sign extending (RV64I)
|
* @brief Add immediate with sign extending (RV64I)
|
| Line 72... |
Line 61... |
* a 32-bit result in rd. Overflows are ignored and the result is the low
|
* a 32-bit result in rd. Overflows are ignored and the result is the low
|
* 32 bits of the result sign-extended to 64 bits. Note, ADDIW rd, rs1, 0
|
* 32 bits of the result sign-extended to 64 bits. Note, ADDIW rd, rs1, 0
|
* writes the sign-extension of the lower 32 bits of register rs1 into
|
* writes the sign-extension of the lower 32 bits of register rs1 into
|
* register rd (assembler pseudo-op SEXT.W).
|
* register rd (assembler pseudo-op SEXT.W).
|
*/
|
*/
|
class ADDIW : public IsaProcessor {
|
class ADDIW : public RiscvInstruction {
|
public:
|
public:
|
ADDIW() : IsaProcessor("ADDIW", "?????????????????000?????0011011") {}
|
ADDIW(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "ADDIW", "?????????????????000?????0011011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
uint64_t imm = u.bits.imm;
|
uint64_t imm = u.bits.imm;
|
if (imm & 0x800) {
|
if (imm & 0x800) {
|
imm |= EXT_SIGN_12;
|
imm |= EXT_SIGN_12;
|
}
|
}
|
data->regs[u.bits.rd] = (data->regs[u.bits.rs1] + imm) & 0xFFFFFFFFLL;
|
R[u.bits.rd] = (R[u.bits.rs1] + imm) & 0xFFFFFFFFLL;
|
if (data->regs[u.bits.rd] & (1LL << 31)) {
|
if (R[u.bits.rd] & (1LL << 31)) {
|
data->regs[u.bits.rd] |= EXT_SIGN_32;
|
R[u.bits.rd] |= EXT_SIGN_32;
|
}
|
|
data->npc = data->pc + 4;
|
|
|
|
if (u.bits.imm == 0) {
|
|
//RISCV_sprintf(data->disasm, sizeof(data->disasm), "sext.w %s,%d",);
|
|
} else {
|
|
//RISCV_sprintf(data->disasm, sizeof(data->disasm), "addiw %s,%s,%d",);
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief Add registers with sign extending (RV64I)
|
* @brief Add registers with sign extending (RV64I)
|
| Line 106... |
Line 90... |
* ADDW is RV64I-only instructions that are defined analogously to
|
* ADDW is RV64I-only instructions that are defined analogously to
|
* ADD but operate on 32-bit values and produce signed 32-bit results.
|
* ADD but operate on 32-bit values and produce signed 32-bit results.
|
* Overflows are ignored, and the low 32-bits of the result is sign-extended
|
* Overflows are ignored, and the low 32-bits of the result is sign-extended
|
* to 64-bits and written to the destination register.
|
* to 64-bits and written to the destination register.
|
*/
|
*/
|
class ADDW : public IsaProcessor {
|
class ADDW : public RiscvInstruction {
|
public:
|
public:
|
ADDW() : IsaProcessor("ADDW", "0000000??????????000?????0111011") {}
|
ADDW(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "ADDW", "0000000??????????000?????0111011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = (R[u.bits.rs1] + R[u.bits.rs2]) & 0xFFFFFFFFLL;
|
(data->regs[u.bits.rs1] + data->regs[u.bits.rs2]) & 0xFFFFFFFFLL;
|
if (R[u.bits.rd] & (1LL << 31)) {
|
if (data->regs[u.bits.rd] & (1LL << 31)) {
|
R[u.bits.rd] |= EXT_SIGN_32;
|
data->regs[u.bits.rd] |= EXT_SIGN_32;
|
|
}
|
}
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief AND bitwise logical operation.
|
* @brief AND bitwise logical operation.
|
*/
|
*/
|
class AND : public IsaProcessor {
|
class AND : public RiscvInstruction {
|
public:
|
public:
|
AND() : IsaProcessor("AND", "0000000??????????111?????0110011") {}
|
AND(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "AND", "0000000??????????111?????0110011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = R[u.bits.rs1] & R[u.bits.rs2];
|
data->regs[u.bits.rs1] & data->regs[u.bits.rs2];
|
return 4;
|
data->npc = data->pc + 4;
|
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief ANDI logical operation with immediate.
|
* @brief ANDI logical operation with immediate.
|
*
|
*
|
* ANDI, ORI, XORI are logical operations that perform bitwise AND, OR,
|
* ANDI, ORI, XORI are logical operations that perform bitwise AND, OR,
|
* and XOR on register rs1 and the sign-extended 12-bit immediate and place
|
* and XOR on register rs1 and the sign-extended 12-bit immediate and place
|
* the result in rd.
|
* the result in rd.
|
*/
|
*/
|
class ANDI : public IsaProcessor {
|
class ANDI : public RiscvInstruction {
|
public:
|
public:
|
ANDI() : IsaProcessor("ANDI", "?????????????????111?????0010011") {}
|
ANDI(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "ANDI", "?????????????????111?????0010011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint64_t imm = u.bits.imm;
|
uint64_t imm = u.bits.imm;
|
if (imm & 0x800) {
|
if (imm & 0x800) {
|
imm |= EXT_SIGN_12;
|
imm |= EXT_SIGN_12;
|
}
|
}
|
|
|
data->regs[u.bits.rd] = data->regs[u.bits.rs1] & imm;
|
R[u.bits.rd] = R[u.bits.rs1] & imm;
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief AUIPC (add upper immediate to pc)
|
* @brief AUIPC (add upper immediate to pc)
|
| Line 171... |
Line 156... |
* AUIPC is used to build pc-relative addresses and uses the U-type
|
* AUIPC is used to build pc-relative addresses and uses the U-type
|
* format. AUIPC forms a 32-bit offset from the 20-bit U-immediate,
|
* format. AUIPC forms a 32-bit offset from the 20-bit U-immediate,
|
* filling in the lowest 12 bits with zeros, adds this offset to the pc,
|
* filling in the lowest 12 bits with zeros, adds this offset to the pc,
|
* then places the result in register rd.
|
* then places the result in register rd.
|
*/
|
*/
|
class AUIPC : public IsaProcessor {
|
class AUIPC : public RiscvInstruction {
|
public:
|
public:
|
AUIPC() : IsaProcessor("AUIPC", "?????????????????????????0010111") {}
|
AUIPC(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "AUIPC", "?????????????????????????0010111") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_U_type u;
|
ISA_U_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
uint64_t off = u.bits.imm31_12 << 12;
|
uint64_t off = u.bits.imm31_12 << 12;
|
if (off & (1LL << 31)) {
|
if (off & (1LL << 31)) {
|
off |= EXT_SIGN_32;
|
off |= EXT_SIGN_32;
|
}
|
}
|
data->regs[u.bits.rd] = data->pc + off;
|
R[u.bits.rd] = icpu_->getPC() + off;
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief The BEQ (Branch if registers are equal)
|
* @brief The BEQ (Branch if registers are equal)
|
*/
|
*/
|
class BEQ : public IsaProcessor {
|
class BEQ : public RiscvInstruction {
|
public:
|
public:
|
BEQ() : IsaProcessor("BEQ", "?????????????????000?????1100011") {}
|
BEQ(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "BEQ", "?????????????????000?????1100011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_SB_type u;
|
ISA_SB_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
if (data->regs[u.bits.rs1] == data->regs[u.bits.rs2]) {
|
if (R[u.bits.rs1] == R[u.bits.rs2]) {
|
uint64_t imm = (u.bits.imm12 << 12) | (u.bits.imm11 << 11)
|
uint64_t imm = (u.bits.imm12 << 12) | (u.bits.imm11 << 11)
|
| (u.bits.imm10_5 << 5) | (u.bits.imm4_1 << 1);
|
| (u.bits.imm10_5 << 5) | (u.bits.imm4_1 << 1);
|
if (u.bits.imm12) {
|
if (u.bits.imm12) {
|
imm |= EXT_SIGN_12;
|
imm |= EXT_SIGN_12;
|
}
|
}
|
data->npc = data->pc + imm;
|
icpu_->setBranch(icpu_->getPC() + imm);
|
} else {
|
|
data->npc = data->pc + 4;
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief The BGE (Branch if greater than or equal using signed comparision)
|
* @brief The BGE (Branch if greater than or equal using signed comparision)
|
| Line 220... |
Line 206... |
* All branch instructions use the SB-type instruction format. The 12-bit
|
* All branch instructions use the SB-type instruction format. The 12-bit
|
* B-immediate encodes signed offsets in multiples of 2, and is added to the
|
* B-immediate encodes signed offsets in multiples of 2, and is added to the
|
* current pc to give the target address. The conditional branch range
|
* current pc to give the target address. The conditional branch range
|
* is ±4 KiB.
|
* is ±4 KiB.
|
*/
|
*/
|
class BGE : public IsaProcessor {
|
class BGE : public RiscvInstruction {
|
public:
|
public:
|
BGE() : IsaProcessor("BGE", "?????????????????101?????1100011") {}
|
BGE(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "BGE", "?????????????????101?????1100011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_SB_type u;
|
ISA_SB_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
if (static_cast<int64_t>(data->regs[u.bits.rs1]) >=
|
if (static_cast<int64_t>(R[u.bits.rs1]) >=
|
static_cast<int64_t>(data->regs[u.bits.rs2])) {
|
static_cast<int64_t>(R[u.bits.rs2])) {
|
uint64_t imm = (u.bits.imm12 << 12) | (u.bits.imm11 << 11)
|
uint64_t imm = (u.bits.imm12 << 12) | (u.bits.imm11 << 11)
|
| (u.bits.imm10_5 << 5) | (u.bits.imm4_1 << 1);
|
| (u.bits.imm10_5 << 5) | (u.bits.imm4_1 << 1);
|
if (u.bits.imm12) {
|
if (u.bits.imm12) {
|
imm |= EXT_SIGN_12;
|
imm |= EXT_SIGN_12;
|
}
|
}
|
data->npc = data->pc + imm;
|
icpu_->setBranch(icpu_->getPC() + imm);
|
} else {
|
|
data->npc = data->pc + 4;
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
|
|
/**
|
/**
|
* @brief The BGEU (Branch if greater than or equal using unsigned comparision)
|
* @brief The BGEU (Branch if greater than or equal using unsigned comparision)
|
*/
|
*/
|
class BGEU : public IsaProcessor {
|
class BGEU : public RiscvInstruction {
|
public:
|
public:
|
BGEU() : IsaProcessor("BGEU", "?????????????????111?????1100011") {}
|
BGEU(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "BGEU", "?????????????????111?????1100011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_SB_type u;
|
ISA_SB_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
if (data->regs[u.bits.rs1] >= data->regs[u.bits.rs2]) {
|
if (R[u.bits.rs1] >= R[u.bits.rs2]) {
|
uint64_t imm = (u.bits.imm12 << 12) | (u.bits.imm11 << 11)
|
uint64_t imm = (u.bits.imm12 << 12) | (u.bits.imm11 << 11)
|
| (u.bits.imm10_5 << 5) | (u.bits.imm4_1 << 1);
|
| (u.bits.imm10_5 << 5) | (u.bits.imm4_1 << 1);
|
if (u.bits.imm12) {
|
if (u.bits.imm12) {
|
imm |= EXT_SIGN_12;
|
imm |= EXT_SIGN_12;
|
}
|
}
|
data->npc = data->pc + imm;
|
icpu_->setBranch(icpu_->getPC() + imm);
|
} else {
|
|
data->npc = data->pc + 4;
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief The BLT (Branch if less than using signed comparision)
|
* @brief The BLT (Branch if less than using signed comparision)
|
*/
|
*/
|
class BLT : public IsaProcessor {
|
class BLT : public RiscvInstruction {
|
public:
|
public:
|
BLT() : IsaProcessor("BLT", "?????????????????100?????1100011") {}
|
BLT(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "BLT", "?????????????????100?????1100011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_SB_type u;
|
ISA_SB_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
if (static_cast<int64_t>(data->regs[u.bits.rs1]) <
|
if (static_cast<int64_t>(R[u.bits.rs1]) <
|
static_cast<int64_t>(data->regs[u.bits.rs2])) {
|
static_cast<int64_t>(R[u.bits.rs2])) {
|
uint64_t imm = (u.bits.imm12 << 12) | (u.bits.imm11 << 11)
|
uint64_t imm = (u.bits.imm12 << 12) | (u.bits.imm11 << 11)
|
| (u.bits.imm10_5 << 5) | (u.bits.imm4_1 << 1);
|
| (u.bits.imm10_5 << 5) | (u.bits.imm4_1 << 1);
|
if (u.bits.imm12) {
|
if (u.bits.imm12) {
|
imm |= EXT_SIGN_12;
|
imm |= EXT_SIGN_12;
|
}
|
}
|
data->npc = data->pc + imm;
|
icpu_->setBranch(icpu_->getPC() + imm);
|
} else {
|
|
data->npc = data->pc + 4;
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief The BLTU (Branch if less than using unsigned comparision)
|
* @brief The BLTU (Branch if less than using unsigned comparision)
|
*/
|
*/
|
class BLTU : public IsaProcessor {
|
class BLTU : public RiscvInstruction {
|
public:
|
public:
|
BLTU() : IsaProcessor("BLTU", "?????????????????110?????1100011") {}
|
BLTU(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "BLTU", "?????????????????110?????1100011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_SB_type u;
|
ISA_SB_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
if (data->regs[u.bits.rs1] < data->regs[u.bits.rs2]) {
|
if (R[u.bits.rs1] < R[u.bits.rs2]) {
|
uint64_t imm = (u.bits.imm12 << 12) | (u.bits.imm11 << 11)
|
uint64_t imm = (u.bits.imm12 << 12) | (u.bits.imm11 << 11)
|
| (u.bits.imm10_5 << 5) | (u.bits.imm4_1 << 1);
|
| (u.bits.imm10_5 << 5) | (u.bits.imm4_1 << 1);
|
if (u.bits.imm12) {
|
if (u.bits.imm12) {
|
imm |= EXT_SIGN_12;
|
imm |= EXT_SIGN_12;
|
}
|
}
|
data->npc = data->pc + imm;
|
icpu_->setBranch(icpu_->getPC() + imm);
|
} else {
|
|
data->npc = data->pc + 4;
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief The BNE (Branch if registers are unequal)
|
* @brief The BNE (Branch if registers are unequal)
|
*/
|
*/
|
class BNE : public IsaProcessor {
|
class BNE : public RiscvInstruction {
|
public:
|
public:
|
BNE() : IsaProcessor("BNE", "?????????????????001?????1100011") {}
|
BNE(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "BNE", "?????????????????001?????1100011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_SB_type u;
|
ISA_SB_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
if (data->regs[u.bits.rs1] != data->regs[u.bits.rs2]) {
|
if (R[u.bits.rs1] != R[u.bits.rs2]) {
|
uint64_t imm = (u.bits.imm12 << 12) | (u.bits.imm11 << 11)
|
uint64_t imm = (u.bits.imm12 << 12) | (u.bits.imm11 << 11)
|
| (u.bits.imm10_5 << 5) | (u.bits.imm4_1 << 1);
|
| (u.bits.imm10_5 << 5) | (u.bits.imm4_1 << 1);
|
if (u.bits.imm12) {
|
if (u.bits.imm12) {
|
imm |= EXT_SIGN_12;
|
imm |= EXT_SIGN_12;
|
}
|
}
|
data->npc = data->pc + imm;
|
icpu_->setBranch(icpu_->getPC() + imm);
|
} else {
|
|
data->npc = data->pc + 4;
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief JAL (Jump and link).
|
* @brief JAL (Jump and link).
|
| Line 351... |
Line 337... |
* register rd. The standard software calling convention uses x1 as the return
|
* register rd. The standard software calling convention uses x1 as the return
|
* address register.
|
* address register.
|
*
|
*
|
* J (pseudo-op) 0 Plain unconditional jumps are encoded as a JAL with rd=x0.
|
* J (pseudo-op) 0 Plain unconditional jumps are encoded as a JAL with rd=x0.
|
*/
|
*/
|
class JAL : public IsaProcessor {
|
class JAL : public RiscvInstruction {
|
public:
|
public:
|
JAL() : IsaProcessor("JAL", "?????????????????????????1101111") {}
|
JAL(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "JAL", "?????????????????????????1101111") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_UJ_type u;
|
ISA_UJ_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint64_t off = 0;
|
uint64_t off = 0;
|
if (u.bits.imm20) {
|
if (u.bits.imm20) {
|
off = 0xfffffffffff00000LL;
|
off = 0xfffffffffff00000LL;
|
}
|
}
|
off |= (u.bits.imm19_12 << 12);
|
off |= (u.bits.imm19_12 << 12);
|
off |= (u.bits.imm11 << 11);
|
off |= (u.bits.imm11 << 11);
|
off |= (u.bits.imm10_1 << 1);
|
off |= (u.bits.imm10_1 << 1);
|
if (u.bits.rd != 0) {
|
if (u.bits.rd != 0) {
|
data->regs[u.bits.rd] = data->pc + 4;
|
R[u.bits.rd] = icpu_->getPC() + 4;
|
}
|
}
|
data->npc = data->pc + off;
|
icpu_->setBranch(icpu_->getPC() + off);
|
if (u.bits.rd == Reg_ra) {
|
if (u.bits.rd == Reg_ra) {
|
if (data->stack_trace_cnt < STACK_TRACE_BUF_SIZE/2) {
|
icpu_->pushStackTrace();
|
data->stack_trace_buf[2*data->stack_trace_cnt] = data->pc;
|
|
data->stack_trace_buf[2*data->stack_trace_cnt] &= ~0x1;
|
|
data->stack_trace_buf[2*data->stack_trace_cnt+1] = data->npc;
|
|
}
|
|
data->stack_trace_cnt++;
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief JALR (Jump and link register).
|
* @brief JALR (Jump and link register).
|
| Line 389... |
Line 372... |
* the register rs1, then setting the least-significant bit of the result to
|
* the register rs1, then setting the least-significant bit of the result to
|
* zero. The address of the instruction following the jump (pc+4) is written
|
* zero. The address of the instruction following the jump (pc+4) is written
|
* to register rd. Register x0 can be used as the destination if the result
|
* to register rd. Register x0 can be used as the destination if the result
|
* is not required.
|
* is not required.
|
*/
|
*/
|
class JALR : public IsaProcessor {
|
class JALR : public RiscvInstruction {
|
public:
|
public:
|
JALR() : IsaProcessor("JALR", "?????????????????000?????1100111") {}
|
JALR(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "JALR", "?????????????????000?????1100111") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint64_t off = u.bits.imm;
|
uint64_t off = u.bits.imm;
|
if (u.bits.imm & 0x800) {
|
if (u.bits.imm & 0x800) {
|
off |= 0xfffffffffffff000LL;
|
off |= 0xfffffffffffff000LL;
|
}
|
}
|
off += data->regs[u.bits.rs1];
|
off += R[u.bits.rs1];
|
off &= ~0x1LL;
|
off &= ~0x1LL;
|
if (u.bits.rd != 0) {
|
if (u.bits.rd != 0) {
|
data->regs[u.bits.rd] = data->pc + 4;
|
R[u.bits.rd] = icpu_->getPC() + 4;
|
}
|
}
|
data->npc = off;
|
icpu_->setBranch(off);
|
|
|
// Stack trace buffer:
|
// Stack trace buffer:
|
if (u.bits.rd == Reg_ra) {
|
if (u.bits.rd == Reg_ra) {
|
if (data->stack_trace_cnt < STACK_TRACE_BUF_SIZE/2) {
|
icpu_->pushStackTrace();
|
data->stack_trace_buf[2*data->stack_trace_cnt] = data->pc;
|
} else if (u.bits.imm == 0 && u.bits.rs1 == Reg_ra) {
|
data->stack_trace_buf[2*data->stack_trace_cnt] &= ~0x1;
|
icpu_->popStackTrace();
|
data->stack_trace_buf[2*data->stack_trace_cnt+1] = data->npc;
|
|
}
|
|
data->stack_trace_cnt++;
|
|
} else if (u.bits.imm == 0 && u.bits.rs1 == Reg_ra
|
|
&& data->stack_trace_cnt) {
|
|
data->stack_trace_cnt--;
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief LOAD instructions (LD, LW, LH, LB) with sign extending.
|
* @brief LOAD instructions (LD, LW, LH, LB) with sign extending.
|
| Line 432... |
Line 411... |
* sign-extended 12-bit offset.
|
* sign-extended 12-bit offset.
|
* The LW instruction loads a 32-bit value from memory into rd. LH loads
|
* The LW instruction loads a 32-bit value from memory into rd. LH loads
|
* a 16-bit value from memory, then sign-extends to 32-bits before storing
|
* a 16-bit value from memory, then sign-extends to 32-bits before storing
|
* in rd.
|
* in rd.
|
*/
|
*/
|
class LD : public IsaProcessor {
|
class LD : public RiscvInstruction {
|
public:
|
public:
|
LD() : IsaProcessor("LD", "?????????????????011?????0000011") {}
|
LD(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "LD", "?????????????????011?????0000011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
Axi4TransactionType trans;
|
Axi4TransactionType trans;
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint64_t off = u.bits.imm;
|
uint64_t off = u.bits.imm;
|
if (off & 0x800) {
|
if (off & 0x800) {
|
off |= EXT_SIGN_12;
|
off |= EXT_SIGN_12;
|
}
|
}
|
trans.source_idx = CFG_NASTI_MASTER_CACHED;
|
|
trans.action = MemAction_Read;
|
trans.action = MemAction_Read;
|
trans.addr = data->regs[u.bits.rs1] + off;
|
trans.addr = R[u.bits.rs1] + off;
|
trans.xsize = 8;
|
trans.xsize = 8;
|
if (trans.addr & 0x7) {
|
if (trans.addr & 0x7) {
|
trans.rpayload.b64[0] = 0;
|
trans.rpayload.b64[0] = 0;
|
generateException(EXCEPTION_LoadMisalign, data);
|
icpu_->raiseSignal(EXCEPTION_LoadMisalign);
|
} else {
|
} else {
|
data->ibus->b_transport(&trans);
|
icpu_->dma_memop(&trans);
|
data->npc = data->pc + 4;
|
|
}
|
|
data->regs[u.bits.rd] = trans.rpayload.b64[0];
|
|
if (data->mem_trace_file) {
|
|
char tstr[512];
|
|
RISCV_sprintf(tstr, sizeof(tstr),
|
|
"%08x: [%08x] => %016" RV_PRI64 "x\n",
|
|
static_cast<int>(data->pc),
|
|
static_cast<int>(trans.addr), trans.rpayload.b64[0]);
|
|
(*data->mem_trace_file) << tstr;
|
|
data->mem_trace_file->flush();
|
|
}
|
}
|
|
R[u.bits.rd] = trans.rpayload.b64[0];
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* Load 32-bits with sign extending.
|
* Load 32-bits with sign extending.
|
*/
|
*/
|
class LW : public IsaProcessor {
|
class LW : public RiscvInstruction {
|
public:
|
public:
|
LW() : IsaProcessor("LW", "?????????????????010?????0000011") {}
|
LW(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "LW", "?????????????????010?????0000011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
Axi4TransactionType trans;
|
Axi4TransactionType trans;
|
trans.source_idx = CFG_NASTI_MASTER_CACHED;
|
|
trans.rpayload.b64[0] = 0;
|
trans.rpayload.b64[0] = 0;
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint64_t off = u.bits.imm;
|
uint64_t off = u.bits.imm;
|
if (off & 0x800) {
|
if (off & 0x800) {
|
off |= EXT_SIGN_12;
|
off |= EXT_SIGN_12;
|
}
|
}
|
trans.action = MemAction_Read;
|
trans.action = MemAction_Read;
|
trans.addr = data->regs[u.bits.rs1] + off;
|
trans.addr = R[u.bits.rs1] + off;
|
trans.xsize = 4;
|
trans.xsize = 4;
|
if (trans.addr & 0x3) {
|
if (trans.addr & 0x3) {
|
trans.rpayload.b64[0] = 0;
|
trans.rpayload.b64[0] = 0;
|
generateException(EXCEPTION_LoadMisalign, data);
|
icpu_->raiseSignal(EXCEPTION_LoadMisalign);
|
} else {
|
} else {
|
data->ibus->b_transport(&trans);
|
icpu_->dma_memop(&trans);
|
data->npc = data->pc + 4;
|
|
}
|
}
|
data->regs[u.bits.rd] = trans.rpayload.b64[0];
|
R[u.bits.rd] = trans.rpayload.b64[0];
|
if (data->regs[u.bits.rd] & (1LL << 31)) {
|
if (R[u.bits.rd] & (1LL << 31)) {
|
data->regs[u.bits.rd] |= EXT_SIGN_32;
|
R[u.bits.rd] |= EXT_SIGN_32;
|
}
|
|
if (data->mem_trace_file) {
|
|
char tstr[512];
|
|
RISCV_sprintf(tstr, sizeof(tstr),
|
|
"%08x: [%08x] => %016" RV_PRI64 "x\n",
|
|
static_cast<int>(data->pc),
|
|
static_cast<int>(trans.addr), trans.rpayload.b64[0]);
|
|
(*data->mem_trace_file) << tstr;
|
|
data->mem_trace_file->flush();
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* Load 32-bits with zero extending.
|
* Load 32-bits with zero extending.
|
*/
|
*/
|
class LWU : public IsaProcessor {
|
class LWU : public RiscvInstruction {
|
public:
|
public:
|
LWU() : IsaProcessor("LWU", "?????????????????110?????0000011") {}
|
LWU(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "LWU", "?????????????????110?????0000011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
Axi4TransactionType trans;
|
Axi4TransactionType trans;
|
trans.source_idx = CFG_NASTI_MASTER_CACHED;
|
|
trans.rpayload.b64[0] = 0;
|
trans.rpayload.b64[0] = 0;
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint64_t off = u.bits.imm;
|
uint64_t off = u.bits.imm;
|
if (off & 0x800) {
|
if (off & 0x800) {
|
off |= EXT_SIGN_12;
|
off |= EXT_SIGN_12;
|
}
|
}
|
trans.action = MemAction_Read;
|
trans.action = MemAction_Read;
|
trans.addr = data->regs[u.bits.rs1] + off;
|
trans.addr = R[u.bits.rs1] + off;
|
trans.xsize = 4;
|
trans.xsize = 4;
|
if (trans.addr & 0x3) {
|
if (trans.addr & 0x3) {
|
trans.rpayload.b64[0] = 0;
|
trans.rpayload.b64[0] = 0;
|
generateException(EXCEPTION_LoadMisalign, data);
|
icpu_->raiseSignal(EXCEPTION_LoadMisalign);
|
} else {
|
} else {
|
data->ibus->b_transport(&trans);
|
icpu_->dma_memop(&trans);
|
data->npc = data->pc + 4;
|
|
}
|
|
data->regs[u.bits.rd] = trans.rpayload.b64[0];
|
|
if (data->mem_trace_file) {
|
|
char tstr[512];
|
|
RISCV_sprintf(tstr, sizeof(tstr),
|
|
"%08x: [%08x] => %016" RV_PRI64 "x\n",
|
|
static_cast<int>(data->pc),
|
|
static_cast<int>(trans.addr), trans.rpayload.b64[0]);
|
|
(*data->mem_trace_file) << tstr;
|
|
data->mem_trace_file->flush();
|
|
}
|
}
|
|
R[u.bits.rd] = trans.rpayload.b64[0];
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* Load 16-bits with sign extending.
|
* Load 16-bits with sign extending.
|
*/
|
*/
|
class LH : public IsaProcessor {
|
class LH : public RiscvInstruction {
|
public:
|
public:
|
LH() : IsaProcessor("LH", "?????????????????001?????0000011") {}
|
LH(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "LH", "?????????????????001?????0000011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
Axi4TransactionType trans;
|
Axi4TransactionType trans;
|
trans.source_idx = CFG_NASTI_MASTER_CACHED;
|
|
trans.rpayload.b64[0] = 0;
|
trans.rpayload.b64[0] = 0;
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint64_t off = u.bits.imm;
|
uint64_t off = u.bits.imm;
|
if (off & 0x800) {
|
if (off & 0x800) {
|
off |= EXT_SIGN_12;
|
off |= EXT_SIGN_12;
|
}
|
}
|
trans.action = MemAction_Read;
|
trans.action = MemAction_Read;
|
trans.addr = data->regs[u.bits.rs1] + off;
|
trans.addr = R[u.bits.rs1] + off;
|
trans.xsize = 2;
|
trans.xsize = 2;
|
if (trans.addr & 0x1) {
|
if (trans.addr & 0x1) {
|
trans.rpayload.b64[0] = 0;
|
trans.rpayload.b64[0] = 0;
|
generateException(EXCEPTION_LoadMisalign, data);
|
icpu_->raiseSignal(EXCEPTION_LoadMisalign);
|
} else {
|
} else {
|
data->ibus->b_transport(&trans);
|
icpu_->dma_memop(&trans);
|
data->npc = data->pc + 4;
|
|
}
|
}
|
data->regs[u.bits.rd] = trans.rpayload.b16[0];
|
R[u.bits.rd] = trans.rpayload.b16[0];
|
if (data->regs[u.bits.rd] & (1LL << 15)) {
|
if (R[u.bits.rd] & (1LL << 15)) {
|
data->regs[u.bits.rd] |= EXT_SIGN_16;
|
R[u.bits.rd] |= EXT_SIGN_16;
|
}
|
|
if (data->mem_trace_file) {
|
|
char tstr[512];
|
|
RISCV_sprintf(tstr, sizeof(tstr),
|
|
"%08x: [%08x] => %016" RV_PRI64 "x\n",
|
|
static_cast<int>(data->pc),
|
|
static_cast<int>(trans.addr), trans.rpayload.b64[0]);
|
|
(*data->mem_trace_file) << tstr;
|
|
data->mem_trace_file->flush();
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* Load 16-bits with zero extending.
|
* Load 16-bits with zero extending.
|
*/
|
*/
|
class LHU : public IsaProcessor {
|
class LHU : public RiscvInstruction {
|
public:
|
public:
|
LHU() : IsaProcessor("LHU", "?????????????????101?????0000011") {}
|
LHU(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "LHU", "?????????????????101?????0000011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
Axi4TransactionType trans;
|
Axi4TransactionType trans;
|
trans.source_idx = CFG_NASTI_MASTER_CACHED;
|
|
trans.rpayload.b64[0] = 0;
|
trans.rpayload.b64[0] = 0;
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint64_t off = u.bits.imm;
|
uint64_t off = u.bits.imm;
|
if (off & 0x800) {
|
if (off & 0x800) {
|
off |= EXT_SIGN_12;
|
off |= EXT_SIGN_12;
|
}
|
}
|
trans.action = MemAction_Read;
|
trans.action = MemAction_Read;
|
trans.addr = data->regs[u.bits.rs1] + off;
|
trans.addr = R[u.bits.rs1] + off;
|
trans.xsize = 2;
|
trans.xsize = 2;
|
if (trans.addr & 0x1) {
|
if (trans.addr & 0x1) {
|
trans.rpayload.b64[0] = 0;
|
trans.rpayload.b64[0] = 0;
|
generateException(EXCEPTION_LoadMisalign, data);
|
icpu_->raiseSignal(EXCEPTION_LoadMisalign);
|
} else {
|
} else {
|
data->ibus->b_transport(&trans);
|
icpu_->dma_memop(&trans);
|
data->npc = data->pc + 4;
|
|
}
|
|
data->regs[u.bits.rd] = trans.rpayload.b16[0];
|
|
if (data->mem_trace_file) {
|
|
char tstr[512];
|
|
RISCV_sprintf(tstr, sizeof(tstr),
|
|
"%08x: [%08x] => %016" RV_PRI64 "x\n",
|
|
static_cast<int>(data->pc),
|
|
static_cast<int>(trans.addr), trans.rpayload.b64[0]);
|
|
(*data->mem_trace_file) << tstr;
|
|
data->mem_trace_file->flush();
|
|
}
|
}
|
|
R[u.bits.rd] = trans.rpayload.b16[0];
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* Load 8-bits with sign extending.
|
* Load 8-bits with sign extending.
|
*/
|
*/
|
class LB : public IsaProcessor {
|
class LB : public RiscvInstruction {
|
public:
|
public:
|
LB() : IsaProcessor("LB", "?????????????????000?????0000011") {}
|
LB(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "LB", "?????????????????000?????0000011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
Axi4TransactionType trans;
|
Axi4TransactionType trans;
|
trans.source_idx = CFG_NASTI_MASTER_CACHED;
|
|
trans.rpayload.b64[0] = 0;
|
trans.rpayload.b64[0] = 0;
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint64_t off = u.bits.imm;
|
uint64_t off = u.bits.imm;
|
if (off & 0x800) {
|
if (off & 0x800) {
|
off |= EXT_SIGN_12;
|
off |= EXT_SIGN_12;
|
}
|
}
|
trans.action = MemAction_Read;
|
trans.action = MemAction_Read;
|
trans.addr = data->regs[u.bits.rs1] + off;
|
trans.addr = R[u.bits.rs1] + off;
|
trans.xsize = 1;
|
trans.xsize = 1;
|
data->ibus->b_transport(&trans);
|
icpu_->dma_memop(&trans);
|
data->regs[u.bits.rd] = trans.rpayload.b8[0];
|
R[u.bits.rd] = trans.rpayload.b8[0];
|
if (data->regs[u.bits.rd] & (1LL << 7)) {
|
if (R[u.bits.rd] & (1LL << 7)) {
|
data->regs[u.bits.rd] |= EXT_SIGN_8;
|
R[u.bits.rd] |= EXT_SIGN_8;
|
}
|
|
data->npc = data->pc + 4;
|
|
if (data->mem_trace_file) {
|
|
char tstr[512];
|
|
RISCV_sprintf(tstr, sizeof(tstr),
|
|
"%08x: [%08x] => %016" RV_PRI64 "x\n",
|
|
static_cast<int>(data->pc),
|
|
static_cast<int>(trans.addr), trans.rpayload.b64[0]);
|
|
(*data->mem_trace_file) << tstr;
|
|
data->mem_trace_file->flush();
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* Load 8-bits with zero extending.
|
* Load 8-bits with zero extending.
|
*/
|
*/
|
class LBU : public IsaProcessor {
|
class LBU : public RiscvInstruction {
|
public:
|
public:
|
LBU() : IsaProcessor("LBU", "?????????????????100?????0000011") {}
|
LBU(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "LBU", "?????????????????100?????0000011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
Axi4TransactionType trans;
|
Axi4TransactionType trans;
|
trans.source_idx = CFG_NASTI_MASTER_CACHED;
|
|
trans.rpayload.b64[0] = 0;
|
trans.rpayload.b64[0] = 0;
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint64_t off = u.bits.imm;
|
uint64_t off = u.bits.imm;
|
if (off & 0x800) {
|
if (off & 0x800) {
|
off |= EXT_SIGN_12;
|
off |= EXT_SIGN_12;
|
}
|
}
|
trans.action = MemAction_Read;
|
trans.action = MemAction_Read;
|
trans.addr = data->regs[u.bits.rs1] + off;
|
trans.addr = R[u.bits.rs1] + off;
|
trans.xsize = 1;
|
trans.xsize = 1;
|
data->ibus->b_transport(&trans);
|
icpu_->dma_memop(&trans);
|
data->regs[u.bits.rd] = trans.rpayload.b8[0];
|
R[u.bits.rd] = trans.rpayload.b8[0];
|
data->npc = data->pc + 4;
|
return 4;
|
if (data->mem_trace_file) {
|
|
char tstr[512];
|
|
RISCV_sprintf(tstr, sizeof(tstr),
|
|
"%08x: [%08x] => %016" RV_PRI64 "x\n",
|
|
static_cast<int>(data->pc),
|
|
static_cast<int>(trans.addr), trans.rpayload.b64[0]);
|
|
(*data->mem_trace_file) << tstr;
|
|
data->mem_trace_file->flush();
|
|
}
|
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief LUI (load upper immediate).
|
* @brief LUI (load upper immediate).
|
*
|
*
|
* It is used to build 32-bit constants and uses the U-type format. LUI places
|
* It is used to build 32-bit constants and uses the U-type format. LUI places
|
* the U-immediate value in the top 20 bits of the destination register rd,
|
* the U-immediate value in the top 20 bits of the destination register rd,
|
* filling in the lowest 12 bits with zeros.
|
* filling in the lowest 12 bits with zeros.
|
*/
|
*/
|
class LUI : public IsaProcessor {
|
class LUI : public RiscvInstruction {
|
public:
|
public:
|
LUI() : IsaProcessor("LUI", "?????????????????????????0110111") {}
|
LUI(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "LUI", "?????????????????????????0110111") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_U_type u;
|
ISA_U_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint64_t tmp = u.bits.imm31_12 << 12;
|
uint64_t tmp = u.bits.imm31_12 << 12;
|
if (tmp & 0x80000000) {
|
if (tmp & 0x80000000) {
|
tmp |= EXT_SIGN_32;
|
tmp |= EXT_SIGN_32;
|
}
|
}
|
data->regs[u.bits.rd] = tmp;
|
R[u.bits.rd] = tmp;
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief OR bitwise operation
|
* @brief OR bitwise operation
|
*/
|
*/
|
class OR : public IsaProcessor {
|
class OR : public RiscvInstruction {
|
public:
|
public:
|
OR() : IsaProcessor("OR", "0000000??????????110?????0110011") {}
|
OR(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "OR", "0000000??????????110?????0110011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = R[u.bits.rs1] | R[u.bits.rs2];
|
data->regs[u.bits.rs1] | data->regs[u.bits.rs2];
|
return 4;
|
data->npc = data->pc + 4;
|
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief OR on register rs1 and the sign-extended 12-bit immediate.
|
* @brief OR on register rs1 and the sign-extended 12-bit immediate.
|
*/
|
*/
|
class ORI : public IsaProcessor {
|
class ORI : public RiscvInstruction {
|
public:
|
public:
|
ORI() : IsaProcessor("ORI", "?????????????????110?????0010011") {}
|
ORI(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "ORI", "?????????????????110?????0010011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
uint64_t imm = u.bits.imm;
|
uint64_t imm = u.bits.imm;
|
if (imm & 0x800) {
|
if (imm & 0x800) {
|
imm |= EXT_SIGN_12;
|
imm |= EXT_SIGN_12;
|
}
|
}
|
data->regs[u.bits.rd] = data->regs[u.bits.rs1] | imm;
|
R[u.bits.rd] = R[u.bits.rs1] | imm;
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief SLLI is a logical left shift (zeros are shifted into the lower bits)
|
* @brief SLLI is a logical left shift (zeros are shifted into the lower bits)
|
*/
|
*/
|
class SLLI : public IsaProcessor {
|
class SLLI : public RiscvInstruction {
|
public:
|
public:
|
SLLI() : IsaProcessor("SLLI", "000000???????????001?????0010011") {}
|
SLLI(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SLLI", "000000???????????001?????0010011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint32_t shamt = u.bits.imm & 0x3f;
|
uint32_t shamt = u.bits.imm & 0x3f;
|
data->regs[u.bits.rd] = data->regs[u.bits.rs1] << shamt;
|
R[u.bits.rd] = R[u.bits.rs1] << shamt;
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief The SLT (signed comparision)
|
* @brief The SLT (signed comparision)
|
*
|
*
|
* It places the value 1 in register rd if rs1 < rs2, 0 otherwise
|
* It places the value 1 in register rd if rs1 < rs2, 0 otherwise
|
*/
|
*/
|
class SLT : public IsaProcessor {
|
class SLT : public RiscvInstruction {
|
public:
|
public:
|
SLT() : IsaProcessor("SLT", "0000000??????????010?????0110011") {}
|
SLT(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SLT", "0000000??????????010?????0110011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
if (static_cast<int64_t>(data->regs[u.bits.rs1]) <
|
if (static_cast<int64_t>(R[u.bits.rs1]) <
|
static_cast<int64_t>(data->regs[u.bits.rs2])) {
|
static_cast<int64_t>(R[u.bits.rs2])) {
|
data->regs[u.bits.rd] = 1;
|
R[u.bits.rd] = 1;
|
} else {
|
} else {
|
data->regs[u.bits.rd] = 0;
|
R[u.bits.rd] = 0;
|
}
|
}
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief The SLTI (set less than immediate)
|
* @brief The SLTI (set less than immediate)
|
*
|
*
|
* It places the value 1 in register rd if register rs1 is less than the
|
* It places the value 1 in register rd if register rs1 is less than the
|
* sign-extended immediate when both are treated as signed numbers, else 0
|
* sign-extended immediate when both are treated as signed numbers, else 0
|
* is written to rd.
|
* is written to rd.
|
*/
|
*/
|
class SLTI : public IsaProcessor {
|
class SLTI : public RiscvInstruction {
|
public:
|
public:
|
SLTI() : IsaProcessor("SLTI", "?????????????????010?????0010011") {}
|
SLTI(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SLTI", "?????????????????010?????0010011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
uint64_t imm = u.bits.imm;
|
uint64_t imm = u.bits.imm;
|
if (imm & 0x800) {
|
if (imm & 0x800) {
|
imm |= EXT_SIGN_12;
|
imm |= EXT_SIGN_12;
|
}
|
}
|
if (static_cast<int64_t>(data->regs[u.bits.rs1]) <
|
if (static_cast<int64_t>(R[u.bits.rs1]) <
|
static_cast<int64_t>(imm)) {
|
static_cast<int64_t>(imm)) {
|
data->regs[u.bits.rd] = 1;
|
R[u.bits.rd] = 1;
|
} else {
|
} else {
|
data->regs[u.bits.rd] = 0;
|
R[u.bits.rd] = 0;
|
}
|
}
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief The SLTU (unsigned comparision)
|
* @brief The SLTU (unsigned comparision)
|
*
|
*
|
* SLTU perform unsigned compares, writing 1 to rd if rs1 < rs2, 0 otherwise.
|
* SLTU perform unsigned compares, writing 1 to rd if rs1 < rs2, 0 otherwise.
|
* @note SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, otherwise
|
* @note SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, otherwise
|
* sets rd to zero (assembler pseudo-op SNEZ rd, rs).
|
* sets rd to zero (assembler pseudo-op SNEZ rd, rs).
|
*/
|
*/
|
class SLTU : public IsaProcessor {
|
class SLTU : public RiscvInstruction {
|
public:
|
public:
|
SLTU() : IsaProcessor("SLTU", "0000000??????????011?????0110011") {}
|
SLTU(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SLTU", "0000000??????????011?????0110011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
if (data->regs[u.bits.rs1] < data->regs[u.bits.rs2]) {
|
if (R[u.bits.rs1] < R[u.bits.rs2]) {
|
data->regs[u.bits.rd] = 1;
|
R[u.bits.rd] = 1;
|
} else {
|
} else {
|
data->regs[u.bits.rd] = 0;
|
R[u.bits.rd] = 0;
|
}
|
}
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief The SLTIU (set less than immediate comparing unsgined values)
|
* @brief The SLTIU (set less than immediate comparing unsgined values)
|
| Line 864... |
Line 786... |
* SLTIU is similar but compares the values as unsigned numbers (i.e., the
|
* SLTIU is similar but compares the values as unsigned numbers (i.e., the
|
* immediate is first sign-extended to 32-bits then treated as an unsigned
|
* immediate is first sign-extended to 32-bits then treated as an unsigned
|
* number). Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals zero, otherwise
|
* number). Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals zero, otherwise
|
* sets rd to 0 (assembler pseudo-op SEQZ rd, rs).
|
* sets rd to 0 (assembler pseudo-op SEQZ rd, rs).
|
*/
|
*/
|
class SLTIU : public IsaProcessor {
|
class SLTIU : public RiscvInstruction {
|
public:
|
public:
|
SLTIU() : IsaProcessor("SLTIU", "?????????????????011?????0010011") {}
|
SLTIU(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SLTIU", "?????????????????011?????0010011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
uint64_t imm = u.bits.imm;
|
uint64_t imm = u.bits.imm;
|
if (imm & 0x800) {
|
if (imm & 0x800) {
|
imm |= EXT_SIGN_12;
|
imm |= EXT_SIGN_12;
|
}
|
}
|
if (data->regs[u.bits.rs1] < imm) {
|
if (R[u.bits.rs1] < imm) {
|
data->regs[u.bits.rd] = 1;
|
R[u.bits.rd] = 1;
|
} else {
|
} else {
|
data->regs[u.bits.rd] = 0;
|
R[u.bits.rd] = 0;
|
}
|
}
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief SLL logical shift left
|
* @brief SLL logical shift left
|
*/
|
*/
|
class SLL : public IsaProcessor {
|
class SLL : public RiscvInstruction {
|
public:
|
public:
|
SLL() : IsaProcessor("SLL", "0000000??????????001?????0110011") {}
|
SLL(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SLL", "0000000??????????001?????0110011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = R[u.bits.rs1] << (R[u.bits.rs2] & 0x3F);
|
data->regs[u.bits.rs1] << (data->regs[u.bits.rs2] & 0x3F);
|
return 4;
|
data->npc = data->pc + 4;
|
|
}
|
}
|
};
|
};
|
|
|
|
|
/**
|
/**
|
* @brief SLLW is a left shifts by register defined value (RV64I).
|
* @brief SLLW is a left shifts by register defined value (RV64I).
|
*/
|
*/
|
class SLLW : public IsaProcessor {
|
class SLLW : public RiscvInstruction {
|
public:
|
public:
|
SLLW() : IsaProcessor("SLLW", "0000000??????????001?????0111011") {}
|
SLLW(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SLLW", "0000000??????????001?????0111011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
data->regs[u.bits.rd] = data->regs[u.bits.rs1] << data->regs[u.bits.rs2];
|
R[u.bits.rd] = R[u.bits.rs1] << R[u.bits.rs2];
|
data->regs[u.bits.rd] &= 0xFFFFFFFFLL;
|
R[u.bits.rd] &= 0xFFFFFFFFLL;
|
if (data->regs[u.bits.rd] & (1LL << 31)) {
|
if (R[u.bits.rd] & (1LL << 31)) {
|
data->regs[u.bits.rd] |= EXT_SIGN_32;
|
R[u.bits.rd] |= EXT_SIGN_32;
|
}
|
}
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief SLLIW is a shifts by a constant (RV64I).
|
* @brief SLLIW is a shifts by a constant (RV64I).
|
*
|
*
|
* SLLIW, SRLIW, and SRAIW are RV64I-only instructions that operate on 32-bit
|
* SLLIW, SRLIW, and SRAIW are RV64I-only instructions that operate on 32-bit
|
* values and produce signed 32-bit results.
|
* values and produce signed 32-bit results.
|
* @exception Illegal_Instruction if imm[5] not equal to 0.
|
* @exception Illegal_Instruction if imm[5] not equal to 0.
|
*/
|
*/
|
class SLLIW : public IsaProcessor {
|
class SLLIW : public RiscvInstruction {
|
public:
|
public:
|
SLLIW() : IsaProcessor("SLLIW", "0000000??????????001?????0011011") {}
|
SLLIW(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SLLIW", "0000000??????????001?????0011011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint32_t shamt = u.bits.imm & 0x1f;
|
uint32_t shamt = u.bits.imm & 0x1f;
|
data->regs[u.bits.rd] = data->regs[u.bits.rs1] << shamt;
|
R[u.bits.rd] = R[u.bits.rs1] << shamt;
|
data->regs[u.bits.rd] &= 0xFFFFFFFFLL;
|
R[u.bits.rd] &= 0xFFFFFFFFLL;
|
if (data->regs[u.bits.rd] & (1LL << 31)) {
|
if (R[u.bits.rd] & (1LL << 31)) {
|
data->regs[u.bits.rd] |= EXT_SIGN_32;
|
R[u.bits.rd] |= EXT_SIGN_32;
|
}
|
}
|
if ((u.bits.imm >> 5) & 0x1) {
|
if ((u.bits.imm >> 5) & 0x1) {
|
generateException(EXCEPTION_InstrIllegal, data);
|
icpu_->raiseSignal(EXCEPTION_InstrIllegal);
|
}
|
}
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief SRA arithmetic shift right
|
* @brief SRA arithmetic shift right
|
*/
|
*/
|
class SRA : public IsaProcessor {
|
class SRA : public RiscvInstruction {
|
public:
|
public:
|
SRA() : IsaProcessor("SRA", "0100000??????????101?????0110011") {}
|
SRA(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SRA", "0100000??????????101?????0110011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
data->regs[u.bits.rd] = static_cast<int64_t>(data->regs[u.bits.rs1])
|
R[u.bits.rd] = static_cast<int64_t>(R[u.bits.rs1])
|
>> (data->regs[u.bits.rs2] & 0x3F);
|
>> (R[u.bits.rs2] & 0x3F);
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief SRAW 32-bits arithmetic shift right (RV64I)
|
* @brief SRAW 32-bits arithmetic shift right (RV64I)
|
*/
|
*/
|
class SRAW : public IsaProcessor {
|
class SRAW : public RiscvInstruction {
|
public:
|
public:
|
SRAW() : IsaProcessor("SRAW", "0100000??????????101?????0111011") {}
|
SRAW(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SRAW", "0100000??????????101?????0111011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
int32_t t1 = static_cast<int32_t>(data->regs[u.bits.rs1]);
|
int32_t t1 = static_cast<int32_t>(R[u.bits.rs1]);
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = static_cast<int64_t>(t1 >> (R[u.bits.rs2] & 0x1F));
|
static_cast<int64_t>(t1 >> (data->regs[u.bits.rs2] & 0x1F));
|
return 4;
|
data->npc = data->pc + 4;
|
|
}
|
}
|
};
|
};
|
|
|
|
|
/**
|
/**
|
* @brief SRAI is an arithmetic right shift.
|
* @brief SRAI is an arithmetic right shift.
|
*
|
*
|
* The original sign bit is copied into the vacanted upper bits.
|
* The original sign bit is copied into the vacanted upper bits.
|
*/
|
*/
|
class SRAI : public IsaProcessor {
|
class SRAI : public RiscvInstruction {
|
public:
|
public:
|
SRAI() : IsaProcessor("SRAI", "010000???????????101?????0010011") {}
|
SRAI(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SRAI", "010000???????????101?????0010011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint32_t shamt = u.bits.imm & 0x3f;
|
uint32_t shamt = u.bits.imm & 0x3f;
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = static_cast<int64_t>(R[u.bits.rs1]) >> shamt;
|
static_cast<int64_t>(data->regs[u.bits.rs1]) >> shamt;
|
return 4;
|
data->npc = data->pc + 4;
|
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief SRAIW arithmetic right shift (RV64I)
|
* @brief SRAIW arithmetic right shift (RV64I)
|
*/
|
*/
|
class SRAIW : public IsaProcessor {
|
class SRAIW : public RiscvInstruction {
|
public:
|
public:
|
SRAIW() : IsaProcessor("SRAIW", "0100000??????????101?????0011011") {}
|
SRAIW(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SRAIW", "0100000??????????101?????0011011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
int32_t t1 = static_cast<int32_t>(data->regs[u.bits.rs1]);
|
int32_t t1 = static_cast<int32_t>(R[u.bits.rs1]);
|
uint32_t shamt = u.bits.imm & 0x1f;
|
uint32_t shamt = u.bits.imm & 0x1f;
|
data->regs[u.bits.rd] = static_cast<int64_t>(t1 >> shamt);
|
R[u.bits.rd] = static_cast<int64_t>(t1 >> shamt);
|
if ((u.bits.imm >> 5) & 0x1) {
|
if ((u.bits.imm >> 5) & 0x1) {
|
generateException(EXCEPTION_InstrIllegal, data);
|
icpu_->raiseSignal(EXCEPTION_InstrIllegal);
|
}
|
}
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
|
|
/**
|
/**
|
* @brief SRL logical shift right
|
* @brief SRL logical shift right
|
*/
|
*/
|
class SRL : public IsaProcessor {
|
class SRL : public RiscvInstruction {
|
public:
|
public:
|
SRL() : IsaProcessor("SRL", "0000000??????????101?????0110011") {}
|
SRL(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SRL", "0000000??????????101?????0110011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = R[u.bits.rs1] >> (R[u.bits.rs2] & 0x3F);
|
data->regs[u.bits.rs1] >> (data->regs[u.bits.rs2] & 0x3F);
|
return 4;
|
data->npc = data->pc + 4;
|
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief SRLI is a logical right shift (zeros are shifted into the upper bits)
|
* @brief SRLI is a logical right shift (zeros are shifted into the upper bits)
|
*/
|
*/
|
class SRLI : public IsaProcessor {
|
class SRLI : public RiscvInstruction {
|
public:
|
public:
|
SRLI() : IsaProcessor("SRLI", "000000???????????101?????0010011") {}
|
SRLI(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SRLI", "000000???????????101?????0010011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint32_t shamt = u.bits.imm & 0x3f;
|
uint32_t shamt = u.bits.imm & 0x3f;
|
data->regs[u.bits.rd] = data->regs[u.bits.rs1] >> shamt;
|
R[u.bits.rd] = R[u.bits.rs1] >> shamt;
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief SRLIW logical right shift (RV64I)
|
* @brief SRLIW logical right shift (RV64I)
|
*/
|
*/
|
class SRLIW : public IsaProcessor {
|
class SRLIW : public RiscvInstruction {
|
public:
|
public:
|
SRLIW() : IsaProcessor("SRLIW", "0000000??????????101?????0011011") {}
|
SRLIW(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SRLIW", "0000000??????????101?????0011011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint32_t shamt = u.bits.imm & 0x1f;
|
uint32_t shamt = u.bits.imm & 0x1f;
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = static_cast<uint32_t>(R[u.bits.rs1]) >> shamt;
|
static_cast<uint32_t>(data->regs[u.bits.rs1]) >> shamt;
|
|
if ((u.bits.imm >> 5) & 0x1) {
|
if ((u.bits.imm >> 5) & 0x1) {
|
generateException(EXCEPTION_InstrIllegal, data);
|
icpu_->raiseSignal(EXCEPTION_InstrIllegal);
|
}
|
}
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief SRLW is a right shifts by register defined value (RV64I).
|
* @brief SRLW is a right shifts by register defined value (RV64I).
|
*/
|
*/
|
class SRLW : public IsaProcessor {
|
class SRLW : public RiscvInstruction {
|
public:
|
public:
|
SRLW() : IsaProcessor("SRLW", "0000000??????????101?????0111011") {}
|
SRLW(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SRLW", "0000000??????????101?????0111011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = R[u.bits.rs1] >> R[u.bits.rs2];
|
data->regs[u.bits.rs1] >> data->regs[u.bits.rs2];
|
R[u.bits.rd] &= 0xFFFFFFFFLL;
|
data->regs[u.bits.rd] &= 0xFFFFFFFFLL;
|
if (R[u.bits.rd] & (1LL << 31)) {
|
if (data->regs[u.bits.rd] & (1LL << 31)) {
|
R[u.bits.rd] |= EXT_SIGN_32;
|
data->regs[u.bits.rd] |= EXT_SIGN_32;
|
|
}
|
}
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief STORE instructions (SD, SW, SH, SB)
|
* @brief STORE instructions (SD, SW, SH, SB)
|
| Line 1103... |
Line 1030... |
* The effective byte address is obtained by adding register rs1 to the
|
* The effective byte address is obtained by adding register rs1 to the
|
* sign-extended 12-bit offset.
|
* sign-extended 12-bit offset.
|
* The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values
|
* The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values
|
* from the low bits of register rs2 to memory.
|
* from the low bits of register rs2 to memory.
|
*/
|
*/
|
class SD : public IsaProcessor {
|
class SD : public RiscvInstruction {
|
public:
|
public:
|
SD() : IsaProcessor("SD", "?????????????????011?????0100011") {}
|
SD(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SD", "?????????????????011?????0100011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
Axi4TransactionType trans;
|
Axi4TransactionType trans;
|
ISA_S_type u;
|
ISA_S_type u;
|
trans.source_idx = CFG_NASTI_MASTER_CACHED;
|
u.value = payload->buf32[0];
|
u.value = payload[0];
|
|
uint64_t off = (u.bits.imm11_5 << 5) | u.bits.imm4_0;
|
uint64_t off = (u.bits.imm11_5 << 5) | u.bits.imm4_0;
|
if (off & 0x800) {
|
if (off & 0x800) {
|
off |= EXT_SIGN_12;
|
off |= EXT_SIGN_12;
|
}
|
}
|
trans.action = MemAction_Write;
|
trans.action = MemAction_Write;
|
trans.xsize = 8;
|
trans.xsize = 8;
|
trans.wstrb = (1 << trans.xsize) - 1;
|
trans.wstrb = (1 << trans.xsize) - 1;
|
trans.addr = data->regs[u.bits.rs1] + off;
|
trans.addr = R[u.bits.rs1] + off;
|
trans.wpayload.b64[0] = data->regs[u.bits.rs2];
|
trans.wpayload.b64[0] = R[u.bits.rs2];
|
if (trans.addr & 0x7) {
|
if (trans.addr & 0x7) {
|
generateException(EXCEPTION_LoadMisalign, data);
|
icpu_->raiseSignal(EXCEPTION_StoreMisalign);
|
} else {
|
} else {
|
data->ibus->b_transport(&trans);
|
icpu_->dma_memop(&trans);
|
data->npc = data->pc + 4;
|
|
}
|
|
if (data->mem_trace_file) {
|
|
char tstr[512];
|
|
RISCV_sprintf(tstr, sizeof(tstr),
|
|
"%08x: [%08x] <= %016" RV_PRI64 "x\n",
|
|
static_cast<int>(data->pc),
|
|
static_cast<int>(trans.addr), trans.wpayload.b64[0]);
|
|
(*data->mem_trace_file) << tstr;
|
|
data->mem_trace_file->flush();
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief Store rs2[31:0] to memory.
|
* @brief Store rs2[31:0] to memory.
|
*/
|
*/
|
class SW : public IsaProcessor {
|
class SW : public RiscvInstruction {
|
public:
|
public:
|
SW() : IsaProcessor("SW", "?????????????????010?????0100011") {}
|
SW(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SW", "?????????????????010?????0100011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
Axi4TransactionType trans;
|
Axi4TransactionType trans;
|
trans.source_idx = CFG_NASTI_MASTER_CACHED;
|
|
trans.wpayload.b64[0] = 0;
|
trans.wpayload.b64[0] = 0;
|
ISA_S_type u;
|
ISA_S_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint64_t off = (u.bits.imm11_5 << 5) | u.bits.imm4_0;
|
uint64_t off = (u.bits.imm11_5 << 5) | u.bits.imm4_0;
|
if (off & 0x800) {
|
if (off & 0x800) {
|
off |= EXT_SIGN_12;
|
off |= EXT_SIGN_12;
|
}
|
}
|
trans.action = MemAction_Write;
|
trans.action = MemAction_Write;
|
trans.xsize = 4;
|
trans.xsize = 4;
|
trans.wstrb = (1 << trans.xsize) - 1;
|
trans.wstrb = (1 << trans.xsize) - 1;
|
trans.addr = data->regs[u.bits.rs1] + off;
|
trans.addr = R[u.bits.rs1] + off;
|
trans.wpayload.b64[0] = data->regs[u.bits.rs2];
|
trans.wpayload.b64[0] = R[u.bits.rs2];
|
if (trans.addr & 0x3) {
|
if (trans.addr & 0x3) {
|
generateException(EXCEPTION_LoadMisalign, data);
|
icpu_->raiseSignal(EXCEPTION_StoreMisalign);
|
} else {
|
} else {
|
data->ibus->b_transport(&trans);
|
icpu_->dma_memop(&trans);
|
data->npc = data->pc + 4;
|
|
}
|
|
if (data->mem_trace_file) {
|
|
char tstr[512];
|
|
RISCV_sprintf(tstr, sizeof(tstr),
|
|
"%08x: [%08x] <= %016" RV_PRI64 "x\n",
|
|
static_cast<int>(data->pc),
|
|
static_cast<int>(trans.addr),
|
|
static_cast<uint64_t>(trans.wpayload.b32[0]));
|
|
(*data->mem_trace_file) << tstr;
|
|
data->mem_trace_file->flush();
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief Store rs2[15:0] to memory.
|
* @brief Store rs2[15:0] to memory.
|
*/
|
*/
|
class SH : public IsaProcessor {
|
class SH : public RiscvInstruction {
|
public:
|
public:
|
SH() : IsaProcessor("SH", "?????????????????001?????0100011") {}
|
SH(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SH", "?????????????????001?????0100011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
Axi4TransactionType trans;
|
Axi4TransactionType trans;
|
trans.source_idx = CFG_NASTI_MASTER_CACHED;
|
|
trans.wpayload.b64[0] = 0;
|
trans.wpayload.b64[0] = 0;
|
ISA_S_type u;
|
ISA_S_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint64_t off = (u.bits.imm11_5 << 5) | u.bits.imm4_0;
|
uint64_t off = (u.bits.imm11_5 << 5) | u.bits.imm4_0;
|
if (off & 0x800) {
|
if (off & 0x800) {
|
off |= EXT_SIGN_12;
|
off |= EXT_SIGN_12;
|
}
|
}
|
trans.action = MemAction_Write;
|
trans.action = MemAction_Write;
|
trans.xsize = 2;
|
trans.xsize = 2;
|
trans.wstrb = (1 << trans.xsize) - 1;
|
trans.wstrb = (1 << trans.xsize) - 1;
|
trans.addr = data->regs[u.bits.rs1] + off;
|
trans.addr = R[u.bits.rs1] + off;
|
trans.wpayload.b64[0] = data->regs[u.bits.rs2] & 0xFFFF;
|
trans.wpayload.b64[0] = R[u.bits.rs2] & 0xFFFF;
|
if (trans.addr & 0x1) {
|
if (trans.addr & 0x1) {
|
generateException(EXCEPTION_LoadMisalign, data);
|
icpu_->raiseSignal(EXCEPTION_StoreMisalign);
|
} else {
|
} else {
|
data->ibus->b_transport(&trans);
|
icpu_->dma_memop(&trans);
|
data->npc = data->pc + 4;
|
|
}
|
|
if (data->mem_trace_file) {
|
|
char tstr[512];
|
|
RISCV_sprintf(tstr, sizeof(tstr),
|
|
"%08x: [%08x] <= %016" RV_PRI64 "x\n",
|
|
static_cast<int>(data->pc),
|
|
static_cast<int>(trans.addr),
|
|
static_cast<uint64_t>(trans.wpayload.b16[0]));
|
|
(*data->mem_trace_file) << tstr;
|
|
data->mem_trace_file->flush();
|
|
}
|
}
|
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief Store rs2[7:0] to memory.
|
* @brief Store rs2[7:0] to memory.
|
*/
|
*/
|
class SB : public IsaProcessor {
|
class SB : public RiscvInstruction {
|
public:
|
public:
|
SB() : IsaProcessor("SB", "?????????????????000?????0100011") {}
|
SB(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SB", "?????????????????000?????0100011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
Axi4TransactionType trans;
|
Axi4TransactionType trans;
|
trans.source_idx = CFG_NASTI_MASTER_CACHED;
|
|
trans.wpayload.b64[0] = 0;
|
trans.wpayload.b64[0] = 0;
|
ISA_S_type u;
|
ISA_S_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
uint64_t off = (u.bits.imm11_5 << 5) | u.bits.imm4_0;
|
uint64_t off = (u.bits.imm11_5 << 5) | u.bits.imm4_0;
|
if (off & 0x800) {
|
if (off & 0x800) {
|
off |= EXT_SIGN_12;
|
off |= EXT_SIGN_12;
|
}
|
}
|
trans.action = MemAction_Write;
|
trans.action = MemAction_Write;
|
trans.xsize = 1;
|
trans.xsize = 1;
|
trans.wstrb = (1 << trans.xsize) - 1;
|
trans.wstrb = (1 << trans.xsize) - 1;
|
trans.addr = data->regs[u.bits.rs1] + off;
|
trans.addr = R[u.bits.rs1] + off;
|
trans.wpayload.b64[0] = data->regs[u.bits.rs2] & 0xFF;
|
trans.wpayload.b64[0] = R[u.bits.rs2] & 0xFF;
|
data->ibus->b_transport(&trans);
|
icpu_->dma_memop(&trans);
|
data->npc = data->pc + 4;
|
return 4;
|
if (data->mem_trace_file) {
|
|
char tstr[512];
|
|
RISCV_sprintf(tstr, sizeof(tstr),
|
|
"%08x: [%08x] <= %016" RV_PRI64 "x\n",
|
|
static_cast<int>(data->pc),
|
|
static_cast<int>(trans.addr),
|
|
static_cast<uint64_t>(trans.wpayload.b8[0]));
|
|
(*data->mem_trace_file) << tstr;
|
|
data->mem_trace_file->flush();
|
|
}
|
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief Subtruction. Overflows are ignored
|
* @brief Subtruction. Overflows are ignored
|
*/
|
*/
|
class SUB : public IsaProcessor {
|
class SUB : public RiscvInstruction {
|
public:
|
public:
|
SUB() : IsaProcessor("SUB", "0100000??????????000?????0110011") {}
|
SUB(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SUB", "0100000??????????000?????0110011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
data->regs[u.bits.rd] = data->regs[u.bits.rs1] - data->regs[u.bits.rs2];
|
R[u.bits.rd] = R[u.bits.rs1] - R[u.bits.rs2];
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief Substruct registers with sign extending (RV64I)
|
* @brief Substruct registers with sign extending (RV64I)
|
| Line 1281... |
Line 1170... |
* SUBW is RV64I-only instructions that are defined analogously to
|
* SUBW is RV64I-only instructions that are defined analogously to
|
* SUB but operate on 32-bit values and produce signed 32-bit results.
|
* SUB but operate on 32-bit values and produce signed 32-bit results.
|
* Overflows are ignored, and the low 32-bits of the result is sign-extended
|
* Overflows are ignored, and the low 32-bits of the result is sign-extended
|
* to 64-bits and written to the destination register.
|
* to 64-bits and written to the destination register.
|
*/
|
*/
|
class SUBW : public IsaProcessor {
|
class SUBW : public RiscvInstruction {
|
public:
|
public:
|
SUBW() : IsaProcessor("SUBW", "0100000??????????000?????0111011") {}
|
SUBW(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "SUBW", "0100000??????????000?????0111011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = (R[u.bits.rs1] - R[u.bits.rs2]) & 0xFFFFFFFFLL;
|
(data->regs[u.bits.rs1] - data->regs[u.bits.rs2]) & 0xFFFFFFFFLL;
|
if (R[u.bits.rd] & (1LL << 31)) {
|
if (data->regs[u.bits.rd] & (1LL << 31)) {
|
R[u.bits.rd] |= EXT_SIGN_32;
|
data->regs[u.bits.rd] |= EXT_SIGN_32;
|
|
}
|
}
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief XOR bitwise operation
|
* @brief XOR bitwise operation
|
*/
|
*/
|
class XOR : public IsaProcessor {
|
class XOR : public RiscvInstruction {
|
public:
|
public:
|
XOR() : IsaProcessor("XOR", "0000000??????????100?????0110011") {}
|
XOR(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "XOR", "0000000??????????100?????0110011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_R_type u;
|
ISA_R_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
data->regs[u.bits.rd] =
|
R[u.bits.rd] = R[u.bits.rs1] ^ R[u.bits.rs2];
|
data->regs[u.bits.rs1] ^ data->regs[u.bits.rs2];
|
return 4;
|
data->npc = data->pc + 4;
|
|
}
|
}
|
};
|
};
|
|
|
/**
|
/**
|
* @brief XOR on register rs1 and the sign-extended 12-bit immediate.
|
* @brief XOR on register rs1 and the sign-extended 12-bit immediate.
|
*
|
*
|
* XORI rd, rs1, -1 performs a bitwise logical inversion of register rs1
|
* XORI rd, rs1, -1 performs a bitwise logical inversion of register rs1
|
* (assembler pseudo-instruction NOT rd, rs).
|
* (assembler pseudo-instruction NOT rd, rs).
|
*/
|
*/
|
class XORI : public IsaProcessor {
|
class XORI : public RiscvInstruction {
|
public:
|
public:
|
XORI() : IsaProcessor("XORI", "?????????????????100?????0010011") {}
|
XORI(CpuRiver_Functional *icpu) :
|
|
RiscvInstruction(icpu, "XORI", "?????????????????100?????0010011") {}
|
|
|
virtual void exec(uint32_t *payload, CpuContextType *data) {
|
virtual int exec(Reg64Type *payload) {
|
ISA_I_type u;
|
ISA_I_type u;
|
u.value = payload[0];
|
u.value = payload->buf32[0];
|
|
|
uint64_t imm = u.bits.imm;
|
uint64_t imm = u.bits.imm;
|
if (imm & 0x800) {
|
if (imm & 0x800) {
|
imm |= EXT_SIGN_12;
|
imm |= EXT_SIGN_12;
|
}
|
}
|
data->regs[u.bits.rd] = data->regs[u.bits.rs1] ^ imm;
|
R[u.bits.rd] = R[u.bits.rs1] ^ imm;
|
data->npc = data->pc + 4;
|
return 4;
|
}
|
}
|
};
|
};
|
|
|
void addIsaUserRV64I(CpuContextType *data, AttributeType *out) {
|
void CpuRiver_Functional::addIsaUserRV64I() {
|
addSupportedInstruction(new ADD, out);
|
addSupportedInstruction(new ADD(this));
|
addSupportedInstruction(new ADDI, out);
|
addSupportedInstruction(new ADDI(this));
|
addSupportedInstruction(new ADDIW, out);
|
addSupportedInstruction(new ADDIW(this));
|
addSupportedInstruction(new ADDW, out);
|
addSupportedInstruction(new ADDW(this));
|
addSupportedInstruction(new AND, out);
|
addSupportedInstruction(new AND(this));
|
addSupportedInstruction(new ANDI, out);
|
addSupportedInstruction(new ANDI(this));
|
addSupportedInstruction(new AUIPC, out);
|
addSupportedInstruction(new AUIPC(this));
|
addSupportedInstruction(new BEQ, out);
|
addSupportedInstruction(new BEQ(this));
|
addSupportedInstruction(new BGE, out);
|
addSupportedInstruction(new BGE(this));
|
addSupportedInstruction(new BGEU, out);
|
addSupportedInstruction(new BGEU(this));
|
addSupportedInstruction(new BLT, out);
|
addSupportedInstruction(new BLT(this));
|
addSupportedInstruction(new BLTU, out);
|
addSupportedInstruction(new BLTU(this));
|
addSupportedInstruction(new BNE, out);
|
addSupportedInstruction(new BNE(this));
|
addSupportedInstruction(new JAL, out);
|
addSupportedInstruction(new JAL(this));
|
addSupportedInstruction(new JALR, out);
|
addSupportedInstruction(new JALR(this));
|
addSupportedInstruction(new LD, out);
|
addSupportedInstruction(new LD(this));
|
addSupportedInstruction(new LW, out);
|
addSupportedInstruction(new LW(this));
|
addSupportedInstruction(new LWU, out);
|
addSupportedInstruction(new LWU(this));
|
addSupportedInstruction(new LH, out);
|
addSupportedInstruction(new LH(this));
|
addSupportedInstruction(new LHU, out);
|
addSupportedInstruction(new LHU(this));
|
addSupportedInstruction(new LB, out);
|
addSupportedInstruction(new LB(this));
|
addSupportedInstruction(new LBU, out);
|
addSupportedInstruction(new LBU(this));
|
addSupportedInstruction(new LUI, out);
|
addSupportedInstruction(new LUI(this));
|
addSupportedInstruction(new OR, out);
|
addSupportedInstruction(new OR(this));
|
addSupportedInstruction(new ORI, out);
|
addSupportedInstruction(new ORI(this));
|
addSupportedInstruction(new SLL, out);
|
addSupportedInstruction(new SLL(this));
|
addSupportedInstruction(new SLLI, out);
|
addSupportedInstruction(new SLLI(this));
|
addSupportedInstruction(new SLLIW, out);
|
addSupportedInstruction(new SLLIW(this));
|
addSupportedInstruction(new SLLW, out);
|
addSupportedInstruction(new SLLW(this));
|
addSupportedInstruction(new SLT, out);
|
addSupportedInstruction(new SLT(this));
|
addSupportedInstruction(new SLTI, out);
|
addSupportedInstruction(new SLTI(this));
|
addSupportedInstruction(new SLTU, out);
|
addSupportedInstruction(new SLTU(this));
|
addSupportedInstruction(new SLTIU, out);
|
addSupportedInstruction(new SLTIU(this));
|
addSupportedInstruction(new SRA, out);
|
addSupportedInstruction(new SRA(this));
|
addSupportedInstruction(new SRAI, out);
|
addSupportedInstruction(new SRAI(this));
|
addSupportedInstruction(new SRAIW, out);
|
addSupportedInstruction(new SRAIW(this));
|
addSupportedInstruction(new SRAW, out);
|
addSupportedInstruction(new SRAW(this));
|
addSupportedInstruction(new SRL, out);
|
addSupportedInstruction(new SRL(this));
|
addSupportedInstruction(new SRLI, out);
|
addSupportedInstruction(new SRLI(this));
|
addSupportedInstruction(new SRLIW, out);
|
addSupportedInstruction(new SRLIW(this));
|
addSupportedInstruction(new SRLW, out);
|
addSupportedInstruction(new SRLW(this));
|
addSupportedInstruction(new SUB, out);
|
addSupportedInstruction(new SUB(this));
|
addSupportedInstruction(new SUBW, out);
|
addSupportedInstruction(new SUBW(this));
|
addSupportedInstruction(new SD, out);
|
addSupportedInstruction(new SD(this));
|
addSupportedInstruction(new SW, out);
|
addSupportedInstruction(new SW(this));
|
addSupportedInstruction(new SH, out);
|
addSupportedInstruction(new SH(this));
|
addSupportedInstruction(new SB, out);
|
addSupportedInstruction(new SB(this));
|
addSupportedInstruction(new XOR, out);
|
addSupportedInstruction(new XOR(this));
|
addSupportedInstruction(new XORI, out);
|
addSupportedInstruction(new XORI(this));
|
|
|
|
/*
|
|
def SLLI_RV32 = BitPat("b0000000??????????001?????0010011")
|
|
def SRLI_RV32 = BitPat("b0000000??????????101?????0010011")
|
|
def SRAI_RV32 = BitPat("b0100000??????????101?????0010011")
|
|
*/
|
/** Base[XLEN-1:XLEN-2]
|
/** Base[XLEN-1:XLEN-2]
|
* 1 = 32
|
* 1 = 32
|
* 2 = 64
|
* 2 = 64
|
* 3 = 128
|
* 3 = 128
|
*/
|
*/
|
data->csr[CSR_misa] = 0x8000000000000000LL;
|
uint64_t isa = 0x8000000000000000LL;
|
data->csr[CSR_misa] |= (1LL << ('I' - 'A'));
|
isa |= (1LL << ('I' - 'A'));
|
}
|
portCSR_.write(CSR_misa, isa);
|
|
|
/**
|
|
* When a trap is taken, the stack is pushed to the left and PRV is set to the
|
|
* privilege mode of the activated trap handler with
|
|
* IE=0.
|
|
*
|
|
* By default, all traps at any privilege level are handled in machine mode,
|
|
* though a machine-mode * handler can quickly redirect traps back to the
|
|
* appropriate level using mrts and mrth instructions (Section 3.2.2).
|
|
* To increase performance, implementations can provide individual read/write
|
|
* bits within mtdeleg to indicate that certain traps should be processed
|
|
* directly by a lower privilege level.
|
|
*
|
|
* The machine trap delegation register (mtdeleg) is an XLEN-bit read/write
|
|
* register that must be implemented, but which can contain a read-only value
|
|
* of zero, indicating that hardware will always direct all traps to machine
|
|
* mode.
|
|
*/
|
|
void generateException(uint64_t code, CpuContextType *data) {
|
|
csr_mcause_type cause;
|
|
cause.value = 0;
|
|
cause.bits.irq = 0;
|
|
cause.bits.code = code;
|
|
data->csr[CSR_mcause] = cause.value;
|
|
data->exception |= 1LL << code;
|
|
}
|
|
|
|
void generateInterrupt(uint64_t code, CpuContextType *data) {
|
|
csr_mcause_type cause;
|
|
cause.value = 0;
|
|
cause.bits.irq = 1;
|
|
cause.bits.code = code;
|
|
data->csr[CSR_mcause] = cause.value;
|
|
data->interrupt = 1;
|
|
}
|
}
|
|
|
} // namespace debugger
|
} // namespace debugger
|
|
|
No newline at end of file
|
No newline at end of file
|
