URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_sysc_plugin/] [riverlib/] [cache/] [dcache.h] - Diff between revs 3 and 4

Rev 3	Rev 4
Line 59...	Line 59...
`sc_signal<sc_uint<BUS_DATA_WIDTH>> dline_data;`	`sc_signal<sc_uint<BUS_DATA_WIDTH>> dline_data;`
`sc_signal<sc_uint<BUS_ADDR_WIDTH>> dline_addr_req;`	`sc_signal<sc_uint<BUS_ADDR_WIDTH>> dline_addr_req;`
`sc_signal<sc_uint<2>> dline_size_req;`	`sc_signal<sc_uint<2>> dline_size_req;`
`sc_signal<sc_uint<2>> state;`	`sc_signal<sc_uint<2>> state;`
`} v, r;`	`} v, r;`
	`bool w_wait_response;`
`};`	`};`


`} // namespace debugger`	`} // namespace debugger`

`#endif // __DEBUGGER_RIVERLIB_DCACHE_H__`	`#endif // __DEBUGGER_RIVERLIB_DCACHE_H__`

`No newline at end of file`	`No newline at end of file`